Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

1EDI2004AS View Datasheet(PDF) - Infineon Technologies

Part Name
Description
MFG CO.
1EDI2004AS
Infineon
Infineon Technologies Infineon
'1EDI2004AS' PDF : 138 Pages View PDF
EiceDRIVERTM SIL
1EDI2004AS
Functional Description
Table 15 Reset Events Summary
Reset Event
Primary Secondary
NRST/RDY Input Reset
signal active
(driven externally)
Soft Reset
UVLO1 Event
Reset
Soft Reset
VCC2 Reset Event -
(communication
loss due to voltage
breakdown on
VCC2; VCC2 < VRST2)
Hard Reset
Notification
(primary)
NRST/RDY Low (during
event).
• Bit PER.RSTE1 and
PER.RST1 set.
• Bit PER.CER1 is not set.
NFLTB activated at the
end of the reset event.
NRST/RDY Low (driven
by device during event).
• Bit PER.RST1 set (once
VCC1 valid again).
• Bit PER.CER1 is not set.
NFLTB activated at the
end of the reset event.
NFLTB activated, bit
PER.CER1 is set.
• Bit PSTAT.SRDY cleared
for the duration of the
failure.
Notification
(secondary)
• Bit SER.CER2 set (in case
of lifesign lost).
• Output Stage issues a
PWM OFF command.
OSD pin functionality
operational.
• Bit SER.CER2 set (in case
of lifesign lost).
• Output Stage issues a
PWM OFF command.
OSD pin functionality
operational.
• Signal NUV2 at Low level
(if VCC2 <VUVLO2).
• Bit SER.RST2 (once VCC2
valid again).
• Output Stage issues a
PWM OFF command.
OSD pin functionality
operational for: VCC2 >
VRST2.
Note:
Reset’s can also happen due to failures, therefore please check the Table 14 “Failure Events
Summary” on Page 48 as well.
Note:
If undervoltage event occur on VCC2, OSD will work until voltage is too less, than automatically
passive clamping will take over. When voltage rising again it behave other way around, but never
both functions operate in parallel.
All reset events set the device in Mode OPM0. In a soft reset, the logic works further, but the registers use the
default values.
In case of a reset condition on the primary side, the behavior of the pin of the device is defined in Table 16.
Table 16 Pin behavior (primary side) in case of reset condition
Pin
Output Level Comments
SDO
Low
NFLTB
Low
NFLTA
High
NRST/RDY
Low (GND1)
Data Sheet
50
Rev. 2.0
2019-01-16
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]