1EDI2004AS View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
'1EDI2004AS' PDF : 138 Pages View PDF
EiceDRIVERTM SIL
1EDI2004AS
Functional Description
2.4.9.3 Memory Supervision
The configuration parameters of the device, stored in the registers, are protected with a parity bit protection
mechanism. Both primary and secondary chips are protected (refer to Chapter 4).
In case a failure is detected on the primary chip, it is kept in reset state, and both signal NRST/RDY and NFLTB
are asserted. The secondary side initiates an Emergency (Regular) Turn-Off sequence.
In case a memory failure is detected by the secondary chip, an Emergency (Regular) Turn-Off sequence is
initiated. The secondary chip is kept in reset state for the duration of the failure. This leads to the detection of
a lifesign error by the primary chip.
2.4.9.4 Hardware Failure Behavior
The internal supervision functions can detect several failures which could lead to primary or secondary chip
hold on (stay in reset). Failures which can be detected are mentioned in the table below. The supervision
functions described in the chapters before will lead to this behavior.
Table 14 Failure Events Summary
Failure Event
Primary Secondary
OSC1 not starting Stay in
Idle
at power-up
Reset
IREF1 shorted to Reset
ground or open
Soft Reset
Memory Error on
Primary
Detected
Hardware
Fail causes
PWM off
Soft Reset
or regular
off
OSC2 not starting Normal
Stay in
at power-up
Operation Reset
OSC2 misfunction
during operation
Detected Soft Reset
Lifesign loss or regular
causes PWM off
off
Notification
(primary)
Notification
(secondary)
• NRST/RDY Low.
• NFLTB activated.
• No SPI communication
possible.
• Output Stage issues a
PWM OFF command.
• OSD pin functionality
operational.
• NRST/RDY Low.
• Bit SER.CER2 set (in case
• NFLTB activated.
of lifesign lost).
• Frequency of OSC1 is out • Output Stage issues a
of range (may lead to SPI PWM OFF command.
communication
• OSD pin functionality
problems).
operational.
• NRST/RDY Low (stays
forever).
• Bit SER.CER2 set (in case
of lifesign lost).
• NFLTB activated.
• Output Stage issues a
PWM OFF command.
• OSD pin functionality
operational.
• NFLTB activated, bit
PER.CER1 is set.
• Output Stage issues a
PWM OFF command.
• Bit PSTAT.SRDY stay 0. • OSD pin functionality
operational.
• NFLTB activated, bit
PER.CER1 is set
• Output Stage issues a
PWM OFF command.
• Bit PSTAT.SRDY cleared • OSD pin functionality
for the duration of the
operational.
failure.
Data Sheet
48
Rev. 2.0
2019-01-16
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