Obsolete Device
24FC65
64K 5.0V 1 MHz I2C™ Smart Serial™ EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Maximum read current 150 µA at 5.5V
- Standby current 1 µA typical
• 1 MHz SE2.bus two wire protocol
• Up to eight devices may be connected to the
same bus for up to 512K bits total memory
• Programmable block security options
• Programmable endurance options
• Schmitt trigger inputs for noise suppression
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles guaranteed for a 4K
block
- 1,000,000 E/W cycles guaranteed for a 60K
block
• Variable page size up to 64 bytes
• 8 byte x 8 line input cache (64 bytes)
for fast write loads
• <3 ms typical write cycle time, byte or page
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24FC65 is a “smart”
8K 8x 8 Serial Electrically Erasable PROM (EEPROM)
with a high-speed 1MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I2C
bus. This device has been developed for advanced
applications such as personal communications, and
provides the systems designer with flexibility through
the use of many new user-programmable features. The
24FC65 offers a relocatable 4K-bit block of
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles
guaranteed. The 24FC65 features an input cache for
fast write loads with a capacity of eight pages, or 64
bytes. This device also features programmable
security options for E/W protection of critical data
and/or code of up to fifteen 4K blocks. Functional
I2C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
2004 Microchip Technology Inc.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
SOIC
A0
1
A1 2
A2 3
VSS
4
8
VCC
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
A0 A1 A2
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
I/O
SCL
SDA
VCC
VSS
XDEC
EEPROM
ARRAY
PAGE LATCHES
CACHE
YDEC
SENSE AMP
R/W CONTROL
address lines allow the connection of up to eight
24FC65's on the same bus for up to 512K bits
contiguous EEPROM memory. The 24FC65 is available
in the standard 8-pin plastic DIP and 8-pin surface
mount SOIC package.
DS21125E-page 1