2ED2109 (4) S06F (J)
650 V half bridge gate driver with integrated bootstrap diode
5.5
Enable or shutdown input
2ED2109 (4) S06F (J) provides an enable functionality that allows to shutdown or to enable the output. When /SD
in pulled up (the enable voltage is higher than VENH) the output is able to operate normally, pulling /SD low (the
enable voltage is lower than VENL) the output is disable. The relationships between the input, output and enable
signals of the 2ED2109 (4) S06F (J) are illustrated below in Figure 7 / 12. From these figures, we can see the
definition of the parameter (i.e. tSD) associated with this device.
Figure 12 Shutdown waveform definitions
5.6
Input logic compatibility
The input pins are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc
supply voltage. Figure 13 illustrates an input signal to the 2ED2109 (4) S06F (J), its input threshold values, and
the logic state of the IC as a result of the input signal. The typical high threshold (VIH) of 2.1 V and typical low
threshold (VIL) of 0.9 V. The input pins are conveniently driven with logic level PWM control signals derived from
3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 0.9 V) offers enhanced noise immunity
compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. 2ED2109 (4)
S06F (J) also features tight control of the input pin threshold voltage levels which eases system design
considerations and ensures stable operation across temperature. The 2ED2109 (4) S06F (J) has input pins that
are capable of sustaining voltages higher than the bias voltage applied on the Vcc pin of the device.
Figure 13 IN & /SD input thresholds
Datasheet
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V 2.022
2020-07-02