9S12HA64 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HA64' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
2.3.64 PIM Reserved Registers
Address 0x0287
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 Read: Always reads 0x00
Write: Unimplemented
Figure 2-62. PIM Reserved Registers
Access: User read1
1
0
0
0
0
0
2.3.65 Port T Interrupt Enable Register (PIET)
Read: Anytime.
Address 0x0288
R
W
Reset
7
PIET7
0
1 Read: Anytime.
Write: Anytime.
6
PIET6
5
PIET5
4
PIET4
3
PIET3
2
PIET2
0
0
0
0
0
Figure 2-63. Port S Interrupt Enable Register (PIES)
Access: User read/write1
1
0
PIET1
PIET0
0
0
Field
7-0
PIET
Table 2-54. PIES Register Field Descriptions
Description
Port T interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.66 Port T Interrupt Flag Register (PIFT)
Address 0x0289
R
W
Reset
7
PIFT7
0
1 Read: Anytime.
Write: Anytime.
6
PIFT6
5
PIFT5
4
PIFT4
3
PIFT3
2
PIFT2
0
0
0
0
0
Figure 2-64. Port S Interrupt Flag Register (PIFS)
Access: User read/write1
1
0
PIFT1
PIFT0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
112
Freescale Semiconductor
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