9S12HA64 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HA64' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
Table 2-59. PIF1AD Register Field Descriptions
Field
Description
7-0
PIF1AD
Port AD interrupt flag—
Each flag is set by an active edge on the associated input pin. To clear this flag, write logic level 1 to the
corresponding bit in the PIF1AD register. Writing a 0 has no effect. 1
1 Active falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
1 In order to enable the Key Wakeup function, need to set the ATDIENL first.
2.3.71 Port R Interrupt Enable Register (PIER)
Read: Anytime.
Address 0x028E
7
R
0
W
Reset
0
1 Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
0
0
PIER3
PIER2
0
0
0
0
0
Figure 2-69. Port R Interrupt Enable Register (PIER)
Access: User read/write1
1
0
PIER1
PIER0
0
0
Field
3-0
PIER
Table 2-60. PIER Register Field Descriptions
Description
Port R interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.72 Port R Interrupt Flag Register (PIFR)
Address 0x028F
7
R
0
W
Reset
0
1 Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
0
0
PIFR3
PIFR2
0
0
0
0
0
Figure 2-70. Port R Interrupt Flag Register (PIFR)
Access: User read/write1
1
0
PIFR1
PIFR0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
115
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