9S12HA64 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HA64' PDF : 790 Pages View PDF
2.3.74 Port U Input Register (PTIU)
Port Integration Module (S12HYPIMV1)
Address 0x0291
7
R PTIU7
6
PTIU6
5
PTIU5
4
PTIU4
3
PTIU3
2
PTIU2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-72. Port U Input Register (PTIU)
1 Read: Anytime.
Write:Never, writes to this register have no effect.
Access: User read1
1
PTIU1
0
PTIU0
u
u
Field
7-0
PTIU
Table 2-63. PTIU Register Field Descriptions
Description
Port U input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.75 Port U Data Direction Register (DDRU)
Address 0x0292
R
W
Reset
7
DDRU7
0
1 Read: Anytime.
Write: Anytime.
6
DDRU6
5
DDRU5
4
DDRU4
3
DDRU3
2
DDRU2
0
0
0
0
0
Figure 2-73. Port U Data Direction Register (DDRU)
Access: User read/write1
1
0
DDRU1
DDRU0
0
0
Table 2-64. DDRU Register Field Descriptions
Field
Description
7,5,3,1 Port U data direction—
DDRU If enabled the Motor driver PWM output it will force the I/O state to be output.
6,4,2,0
DDRU
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
Else if corresponding TIM0 output compare channel is enabled, it will be force as output
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
117
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