A3985SLDTR-T View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A3985SLDTR-T' PDF : 15 Pages View PDF
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Note that, for tFD > tOFF , the device effectively operates in
full fast-decay mode.
D12 and D13 – Master Clock Control An internal
oscillator can be used for the timing functions, and if more
precise control is required, an external clock can be input to
the OSC terminal (for configuration information, refer to the
Functional Description section). To accommodate a wider
range of external system clocks, an internal divider is pro-
vided to generate the desired master clock frequency, fMCK ,
according to the following table:
D13 D12
0
0
Master Clock Source and fMCK
Internal oscillator*
0
1
External clock rate
1
0
External clock rate / 2
1
1
External clock rate / 4
*4 MHz typical, configurable with external resistor, ROSC.
D14 and D15 – Synchronous Rectification Two bits
are used to set the mode for sunchronous rectification. The
modes are described in the synchronous rectification section
of the Functional Description section.
D15 D14
0
0
Synchronous
Rectification Mode
Disabled
0
1
1
0
Disabled
Active
1
1
Passive
D16 and D17 – Reserved These bits are reserved for test-
ing and should be programmed to 0 during normal operation.
D18 – Idle Mode The device can be placed in a low power
mode by writing a 0 to D18. This disables the outputs and
the device draws a lower load supply current. The undervolt-
age monitor circuit remains active. When leaving idle mode,
D18 should be set to 1 for 1 ms before attempting to enable
any output driver.
Bit Assignments Table
Word
Data Register
Bit
Function
D0 Register Select = 0
D1 Bridge 1, DAC bit 0 (LSB)
D2 Bridge 1, DAC bit 1
D3 Bridge 1, DAC bit 2
D4 Bridge 1, DAC bit 3
D5 Bridge 1, DAC bit 4
D6 Bridge 1, DAC bit 5 (MSB)
D7 Bridge 1, Phase
D8 Bridge 1, Mode
0
D9 Bridge 2, DAC bit 0 (LSB)
D10 Bridge 2, DAC bit 1
D11 Bridge 2, DAC bit 2
D12 Bridge 2, DAC bit 3
D13 Bridge 2, DAC bit 4
D14 Bridge 2, DAC bit 5 (MSB)
D15 Bridge 2, Phase
D16 Bridge 2, Mode
D17 Range Select bit 0
D18 Range Select bit 1
Word Bit
Control Register
Function
D0 Register Select = 1
D1 Blank-time bit 0 (LSB)
D2 Blank-time bit 1 (MSB)
D3 Off-time bit 0 (LSB)
D4 Off-time bit 1
D5 Off-time bit 2
D6 Off-time bit 3
D7 Off-time bit 4 (MSB)
D8 Fast-decay time bit 0 (LSB)
1
D9 Fast-decay time bit 1
D10 Fast-decay time bit 2
D11 Fast-decay time bit 3 (MSB)
D12 Master Clock Control bit 0 (LSB)
D13 Master Clock Control bit 1 (MSB)
D14 Synchronous Rectification Control bit 0 (LSB)
D15 Synchronous Rectification Control bit 1 (MSB)
D16 Reserved
D17 Reserved
D18 Idle Mode
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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