A4980LP View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A4980LP' PDF : 44 Pages View PDF
A4980
Automotive, Programmable Stepper Driver
as 3.5 V without disabling the outputs. By retaining the higher
threshold (when VBB is above the VBB undervoltage threshold),
the A4980 also provides protection for its outputs from excessive
power dissipation during a high voltage transient on VBB when
an independent VREG undervoltage condition is present.
Note that the point at which the A4980 stops driving the motor
is always less than 3.5 V. The maximum value for the low-level
VREG undervoltage threshold is 3.15 V, and for the VREG drop-
out, it is 200 mV. This means that the VREG undervoltage will
never occur until VBB falls below 3.3 V, giving a 200 mV margin
for noise. Typically the VREG undervoltage will occur when
VBB drops below 3.1 V. The A4980 will continue with full PWM
current control and all output fault detection down to the point at
which the VREG undervoltage fault occurs.
drops below the VDD undervoltage threshold). The threshold will
remain at the high level, irrespective of the state of VBB , until the
VBB voltage has exceeded the undervoltage threshold for the first
time. After this has happened, the VREG undervoltage threshold
is then determined by the state of the VBB undervoltage monitor
output. When applying power or when activating from sleep mode
the outputs should remain inactive for at least the Wakeup from
Figures 3 and 4 show how the undervoltage thresholds change
when a typical cold crank transient occurs.
The standard, ISO7637 Pulse 4, is shown for reference in
figure 3. The VBB transient shown (solid line) is lower than the
standard ISO pulse due to the forward voltage of a reverse polar-
ity protection diode and switching transients.
Figure 4 provides more detail around the time that the VBB
undervoltage is detected. It shows the VREG voltage follow-
ing below the VBB voltage by the maximum offset voltage of
the VREG regulator. Typically this dropout will be less than the
200 mV shown.
When VBB drops below the falling VBB undervoltage threshold,
VBBUV (at 1.2 ms and 5.6 V in figure 4), the VREG undervoltage
threshold, VREGUV , drops from 4.8 V (VREGUVH typical) to 3.0 V
(VREGUVL typical). At the same time, the VBB undervoltage
threshold increases by the threshold hysteresis, 760 mV (typical),
the UV fault bit in the diagnostic registers is set, and the fault flag
is active.
Figure 3. A4980 response to an undervoltage transient
This state remains until VBB increases above the rising VBB
undervoltage threshold (at 127 ms and 6.4 V in figure 3). At this
point the VREG undervoltage threshold is increased back to the
high threshold value of 4.8 V (VREGUVH typical), and the reverse
hysteresis is applied to the VBB undervoltage threshold causing
it to drop back to the falling level of 5.5 V (VBBUV typical). The
Fault flag goes inactive but the UV fault bit remains set in the
Fault registers until cleared by a diagnostic registers reset.
When a power-on reset occurs, or the A4980 is activated from
sleep mode by taking RESETn high, then the VREG undervoltage
threshold is initially set to the high level, VREGUVH . (A power-on
reset occurs when power is first applied or the logic supply, VDD ,
Figure 4. Expanded view of figure 3
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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