A4980LP View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A4980LP' PDF : 44 Pages View PDF
A4980
Automotive, Programmable Stepper Driver
Serial Interface Description
A three wire synchronous serial interface, compatible with
SPI, can be used to configure and control all the features of the
A4980. A fourth wire can be used to provide diagnostic feedback.
The registers that are accessible through the serial interface are
defined in table 2.
The A4980 can be operated without using the serial interface,
by using the default configuration and control register settings
and the STEP and DIR logic inputs for motor control. However,
application-specific configurations are only possible by setting
the appropriate register bits through the serial interface. In addi-
tion to setting the configuration bits, the serial interface can also
be used to control the motor directly.
The serial interface timing requirements are specified in the Elec-
trical Characteristics table, and illustrated in figure 1.
Writing to Configuration and Control Registers
When writing to the serial register, data is received on the SDI
pin and clocked through a shift register on the rising edge of the
clock signal input on the SCK pin. STRn is normally held high,
and is only brought low to initiate a serial transfer. No data is
clocked through the shift register when STRn is high, thus allow-
ing multiple SDI slave units to use common SDI, SCK, and SDO
connections. Each independent slave requires a dedicated STRn
connection.
The serial data word has 16 bits, MSB input first. After 16 data
bits have been clocked into the shift register, STRn must be taken
high to latch the data into the selected register. When this occurs,
Table 2. Serial Register Definition*
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Configuration and Control Registers (Write)
Configuration
Register 0
0
(CONFIG0)
SYR MS1 MS0
0
1
0
0
MXI1
1
MXI0
1
PFD2
1
PFD1
0
PFD0
0
TBK1
0
TBK0
1
TOF2
FRQ2
1
TOF1
FRQ1
1
TOF0
FRQ0
0
PWM
0
Configuration
OSC TSC1 TSC0
CD3 CD2 CD1 CD0 DIAG1 DIAG0
Register 1
0
1
(CONFIG1)
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Run Register
(RUN)
1
EN OL1 OL0 HLR SLEW BRK DCY1 DCY0 SC5 SC4 SC3 SC2 SC1 SC0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
Table Load
PTP PT5 PT4 PT3 PT2 PT1 PT0
Register
1
1
(TBLLD)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Diagnostic Registers (Read)
Fault
Register 0
(FAULT0)
FF TW1 TW0 OV UV ST
Fault
Register 1
FF TW1 TW0 OV
UV
ST
(FAULT1)
*Power-on reset value shown below each input register bit.
OLB OLA BML BMH BPL BPH AML AMH APL APH
OLB OLA
0
0
SA5 SA4 SA3 SA2 SA1 SA0
Allegro MicroSystems, Inc.
16
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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