AC206-DS02-R View Datasheet(PDF) - Broadcom Corporation
Part Name
Description
MFG CO.
'AC206-DS02-R' PDF : 70 Pages View PDF
Preliminary Data Sheet
07/08/02
AC206
PHY REGISTERS
The following registers are defined for each PHY port. The base addresses of PHY 1 to PHY 8 are 0, 1, 2, 3, 4, 5, 6, and 7,
respectively.
PHY CONFIGURATION REGISTER
Bit
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6:0
Name
Reset
Loopback
Speed Select
Auto-Neg Enable
Power Down
Isolate
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Reserved
Table 22: PHY Configuration Register 0
Definition
1 = PHY reset
This bit is self-clearing.
1 = Loopback mode. Because it internally loops the transmit of
AC206 to its receive, it ignores all the activity on the cable media.
0 = Normal operation.
1 = 100 Mbps
0 = 10 Mbps. This bit is ignored if auto-negotiation is enabled.
It no longer reflects auto-negotiation results.
1 = Enable auto-negotiate process (overrides 0.13 and 0.8)
0 = Disable auto-negotiate process.
In force mode, speed is selected via bit 0.13.
1 = Power down mode, puts AC206 in low-power stand-by mode,
only react to access transaction.
0 = Normal operation.
1 = Electrical isolation of PHY from MII and cable media.
0 = Normal operation.
1 = Restart auto-negotiation process.
0 = Normal operation.
1 = Full-duplex.
0 = Half-duplex.
Full-duplex is not supported on this chip. It no longer reflects the
auto-negotiation result.
1 = Enable collision test, which issues the COL signal in
response to the assertion of TX_EN signal.
0 = Disable COL test.
Mode
RW/SC
RW
RW
RW
RW
RW
RW/
SC
RO
RW
RO
Default
0
0
1
1
0
0
0
0
0
000000
Document AC206-DS05-405-R
Broadcom
PHY Registers Page 23
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