ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 22 (continued)
Bit No.
Description
[3:0]
reference_source_frequency_<n>
Programs the frequency of the reference source
connected to input I<n>. If divn_<n> is set, then this
value should be set to 0000 (8 kHz).
Bit Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
Value Description
8 kHz.
1544/2048 kHz dependant on bit 2 in register 34
6.48 MHz.
19.44 MHz.
25.92 MHz.
38.88 MHz.
51.84 MHz.
77.76 MHz.
155.52 MHz.
2 kHz.
4 kHz.
Not used.
Address(hex): 30
Register Name cnfg_sts_remote_sources_valid
Bit 7
Bit 6
Bit 5
Description
Bit 4
(R/W) Bits [7:0] of the remote
Default Value
sources valid register. A register used
to disable sources that are invalid in
another device in a redundancy pair.
Bit 3
Bit 2
Bit 1
1111 1111
Bit 0
I8
I7
I6
I5
I4
I3
I2
I1
Bit No.
Description
Bit Value Value Description
7
I8 - Bit enabling input I8 to be considered for locking
0
Locking to input I8 disallowed.
to. If this bit is not set, then even if this input I8 is
1
Locking to input I8 allowed.
valid, it will still not appear in register 0A & 0B.
6
I7 - Bit enabling input I7 to be considered for locking
0
Locking to input I7 disallowed.
to. If this bit is not set, then even if this input I7 is
1
Locking to input I7 allowed.
valid, it will still not appear in register 0A & 0B.
5
I6 - Bit enabling input I6 to be considered for locking
0
Locking to input I6 disallowed.
to. If this bit is not set, then even if this input I6 is
1
Locking to input I6 allowed.
valid, it will still not appear in register 0A & 0B.
4
I5 - Bit enabling input I5 to be considered for locking
0
Locking to input I5 disallowed.
to. If this bit is not set, then even if this input I5 is
1
Locking to input I5 allowed.
valid, it will still not appear in register 0A & 0B.
3
I4 - Bit enabling input I4 to be considered for locking
0
Locking to input I4 disallowed.
to. If this bit is not set, then even if this input I4 is
1
Locking to input I4 allowed.
valid, it will still not appear in register 0A & 0B.
2
I3 - Bit enabling input I3 to be considered for locking
0
Locking to input I3 disallowed.
to. If this bit is not set, then even if this input I3 is
1
Locking to input I3 allowed.
valid, it will still not appear in register 0A & 0B.
1
I2 - Bit enabling input I2 to be considered for locking
0
Locking to input I2 disallowed.
to. If this bit is not set, then even if this input I2 is
1
Locking to input I2 allowed.
valid, it will still not appear in register 0A & 0B.
0
I1 - Bit enabling input I1 to be considered for locking
0
Locking to input I1 disallowed.
to. If this bit is not set, then even if this input I1 is
1
Locking to input I1 allowed.
valid, it will still not appear in register 0A & 0B.
Revision 3.00 April 2007 © Semtech Corp.
Page 43
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