ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 41
Register Name cnfg_DPLL_freq_limit
[7:0]
Bit 7
Bit 6
Bit 5
Description
Bit 4
(R/W) Bits [7:0] of the DPLL
frequency limit register.
Bit 3
Bit 2
Default Value 0111 0110
Bit 1
Bit 0
DPLL_freq_limit_value[7:0]
Bit No.
Description
Bit Value Value Description
[7:0]
DPLL_freq_limit_value[7:0]
This register defines the extent of frequency offset
to which either the Monitor or the T4 DPLL will track
a source before limiting- i.e. it represents the pull-in
range of the DPLLs. The offset of the device is
determined by the frequency offset of the DPLL
when compared to the offset of the external crystal
oscillator clocking the device. If the oscillator is
calibrated using register 3C & 3D, then this
calibration is automatically taken into account. The
DPLL frequency limit limits the offset of the DPLL
when compared to the calibrated oscillator
frequency.
-
In order to calculate the frequency limit in ppm,
bits[1:0] of register 42h & bits[7:0] of register
41h need to be concatenated. This value is a
unsigned integer and represents the limit, both
positive and negative, in ppm. The value
multiplied by 0.078 will give the value in ppm.
Address(hex): 42
Register Name cnfg_DPLL_freq_limit Description (R/W) Bits [9:8] of the DPLL frequency limit register.
[9:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0000
Bit 0
DPLL_freq_limit_value[9:8]
Bit No. Description
Bit Value
Value Description
[7:2]
Not used.
-
-
[1:0]
DPLL_freq_limit_value[9:8]
-
See register 41 (cnfg_DPLL_freq_limit.) for details.
Address(hex): 43
Register Name
Bit 7
cnfg_interrupt_mask
[7:0]
Bit 6
Bit 5
Description (R/W) Bits [7:0] of the interrupt mask register.
Bit 4
Bit 3
Bit 2
Default Value 0000 0000
Bit 1
Bit 0
I8
I7
I6
I5
I4
I3
I2
I1
Bit No.
Description
Bit Value
Value Description
7
I8
Mask bit for input I8 interrupt.
6
I7
Mask bit for input I7 interrupt.
5
I6
Mask bit for input I6 interrupt.
0
Input I8 cannot generate interrupts.
1
Input I8 can generate interrupts.
0
Input I7 cannot generate interrupts.
1
Input I7 can generate interrupts.
0
Input I6 cannot generate interrupts.
1
Input I6 can generate interrupts.
Revision 3.00 April 2007 © Semtech Corp.
Page 50
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