ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 64
Register Name cnfg_T4_DPLL_frequency
Bit 7
Bit 6
Bit 5
Description
Bit 4
(R/W) Register to configure the
T4 DPLL and several other
parameters for the T4 path.
Bit 3
Bit 2
Default Value 0000 0001
Bit 1
Bit 0
Bit No.
Auto_squelch_
T4
Description
AMI_op_duty
T4_op_
SONSDH
Bit Value
T4_DPLL_Enable
Value Description
7, 3
Not used.
-
-
6
Auto_squelch_T4
Register bit to automatically squelch the T4 outputs
on TO1 and TO2 when the T4 inputs have failed.
0
Outputs TO1 and TO2 enabled as in register 63h
1
Outputs TO1 and TO2 disabled when T4 inputs
fail.
5
AMI_op_duty
Register bit to configure whether the composite
clock output of TO2 is 50:50 or 5:8 duty cycle.
0
TO2 output 50:50 duty cycle.
1
TO2 output 5:8 duty cycle.
4
T4_op_SONSDH
0
TO1 output 2.048 MHz (SDH).
Register bit to configure the BITS output on TO1 to
1
TO1 output 1.544 MHz (SONET).
be either SONET or SDH frequency.
Check that register 35h, bit 4 is set to 0, otherwise
this bit is ignored and SONET/SDH selection for TO1
is controlled by register 34h, bit 2.
Default set by SONSDHB pin - same as register 34
bit 2.
[2:0]
T4_DPLL_frequency
Register to control the system clock driving the T4
DPLL
000
001
010- 111
T4 DPLL squelched (clock off).
T4 DPLL enabled (clock on).
Do Not Use
Address(hex): 65
Register Name cnfg_T4_meas_phase
Bit 7
Bit 6
Bit 5
Description
Bit 4
(R/W) Register to configure the
T4 phase detector to measure
the phase between 2 inputs
Bit 3
Bit 2
Default Value 0000 0001
Bit 1
Bit 0
T4_meas_phas Set to 0
Set to 0
Set to 0
Set to 1
Bit No.
Description
Bit Value Value Description
7
T4_meas_phas
0
Normal- T4 Path normal operation.
Register bit to control the feature to use the T4 path
1
T4 DPLL disabled, T4 phase detector used to
to measure phase difference between the Monitor
measure phase between selected Monitor
DPLL input and the selected T4 input.
DPLL input and the selected T4 input.
6, 2, 1
Set to 0
0
-
5,4,3
0
Not used.
Set to 1
0
-
1
-
Revision 3.00 April 2007 © Semtech Corp.
Page 65
www.semtech.com
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