ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 73
Register Name cnfg_phase_loss_limit
Bit 7
Bit 6
Bit 5
Description
Bit 4
(R/W) Register to configure some Default Value
of the parameters of the Monitor
DPLL phase detector.
Bit 3
Bit 2
Bit 1
1010 0010
Bit 0
fine_limit_en noact_ph_loss narrow_en
phase_loss_fine_limit
Bit No.
Description
Bit Value Value Description
7
fine_limit_en
Register bit to enable the phase_loss_fine_limit Bits
[2:0]. When disabled, phase lock/loss is determined
by the other means within the device. This must be
disabled when multi-UI jitter tolerance is required,
see register 74h, cnfg_phase_loss_course_limit .
6
noact_ph_loss
The DPLL detects that an input has failed very
rapidly. Normally, when the DPLL detects this
condition, it does not consider phase lock to be lost
and will phase lock to the nearest edge (±180º)
when a source becomes available again, hence
giving tolerance to missing cycles. If phase loss is
indicated, then frequency and phase locking is
instigated (±360º locking). This bit can be used to
force the DPLL to indicate phase loss immediately
when no activity is detected.
5
narrow_en (test control bit)
Set to 1 (default value)
[4:3]
Not used.
0
Phase loss indication only triggered by other
means.
1
Phase loss triggered when phase error exceeds
the limit programmed in phase_loss_fine_limit ,
Bits [2:0].
0
No activity on reference does not trigger phase
lost indication.
1
No activity triggers phase lost indication.
It is recommended that it should be set = 1
when use is made of the T4_DPLL_Lock lock
indication bit (register 09h, bit 6).
0
1
Set to 1
-
-
[2:0]
phase_loss_fine_limit
When enabled by Bit 7, this register coarsely sets
the phase limit at which the device indicates phase
lost or locked. The default value of 2 (010) gives a
window size of around ±(90º to 180º). The phase
position of the inputs to the DPLL has to be within
the window limit for 1 to 2 seconds before the
device indicates phase lock. If it is outside the
window for any time then phase loss is immediately
indicated. For most cases the default value of 2
(010) is satisfactory. The window size changes in
proportion to the value, so a value of 1 (001) will
give a narrow phase acceptance or lock window of
approximately ±(45º to 90º).
000
Do not use. Indicates phase loss continuously.
001
Small phase window for phase lock indication.
010
Recommended value.
011
)
100
)
101
) Larger phase window for phase lock indication.
110
)
111
)
Revision 3.00 April 2007 © Semtech Corp.
Page 68
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