ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 74
Register Name cnfg_phase_loss_coarse_limit Description
Bit 7
Bit 6
Bit 5
Bit 4
(R/W) Register to configure some Default Value
of the parameters of the Monitor
DPLL phase detector.
Bit 3
Bit 2
Bit 1
1000 0101
Bit 0
coarse_lim-
phaseloss_en
Bit No.
wide_range_en multi_ph_resp
Description
phase_loss_coarse_limit
Bit Value Value Description
7
coarse_lim_phaseloss_en
0 Phase loss not triggered by the coarse
Register bit to enable the coarse phase detector, whose range is
phase lock detector.
determined by phase_loss_coarse_limit Bits [3:0]. This register
1 Phase loss triggered when phase error
sets the limit in the number of input clock cycles (UI) that the
exceeds the limit programmed in
input phase can move by before the DPLL indicates phase lost.
phase_loss_coarse_limit , Bits [3:0].
6
wide_range_en
0 Wide range phase detector off.
To enable the device to be tolerant to large amounts of applied
1 Wide range phase detector on.
jitter and still do direct phase locking at the input frequency rate
(up to 77.76 MHz), a wide range phase detector and phase lock
detector is employed. This bit enables the wide range phase
detector. This allows the device to be tolerant to, and therefore
keep track of, drifts in input phase of many cycles (UI). The range
of the phase detector is set by the same register used for the
phase loss coarse limit (Bits [3:0]).
5
multi_ph_resp
0 DPLL phase detector limited to ±360º (±1
Enables the phase result from the coarse phase detector to be
UI). However it will still remember its
used in the DPLL algorithm. Bit 6 should also be set when this is
original phase position over many
activated. The coarse phase detector can measure and keep
thousands of UI if Bit 6 is set.
track over many thousands of input cycles, thus allowing
1
excellent jitter and wander tolerance. This bit enables that phase
DPLL phase detector also uses the full
result to be used in the DPLL algorithm, so that a large phase
coarse phase detector result. It can now
measurement gives a faster pull-in of the DPLL. If this bit is not
measure up to:
set then the phase measurement is limited to ±360º which can
±360º X 8191 UI = ±2,948,760º.
give a slower pull-in rate at higher input frequencies, but could
also be used to give less overshoot.
Setting this bit in direct locking mode, for example
with a 19.44 MHz input, could be used to give the same dynamic
response as a 19.44 MHz input used with 8 k locking mode,
where the input is divided down internally to 8 kHz first.
4
Not used.
-
-
[3:0]
phase_loss_coarse_limit
0000 Input phase error tracked over ±1 UI.
Sets the range of the coarse phase loss detector and the coarse 0001 Input phase error tracked over ±3 UI.
phase detector.
0010 Input phase error tracked over ±7 UI.
When locking to a high frequency signal and jitter tolerance
0011 Input phase error tracked over ±15 UI.
greater than ± 0.5 UI is required, then the DPLL can be
0100 Input phase error tracked over ±31 UI.
configured to track phase errors over many input clock periods.
0101 Input phase error tracked over ±63 UI.
This is particularly useful with very low bandwidths. This register 0110 Input phase error tracked over ±127 UI.
configures how many UI over which the input phase can be
0111 Input phase error tracked over ±255 UI.
tracked. It also sets the range of the coarse phase loss detector, 1000 Input phase error tracked over ±511 UI.
which can be used with or without the multi-UI phase capture
1001 Input phase error tracked over ±1023 UI.
range capability.
1010 Input phase error tracked over ±2047 UI.
This register value is used by Bits 6 and 7.
1011 Input phase error tracked over ±4095 UI.
1100- Input phase error tracked over ±8191 UI.
1111
Revision 3.00 April 2007 © Semtech Corp.
Page 69
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