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ACS8514T View Datasheet(PDF) - Semtech Corporation

Part Name
Description
MFG CO.
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Electrical Specifications
JTAG
The JTAG connections on the ACS8514 allow a full
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1[5], with the following minor
exceptions, and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture
data from the core, and so do not support INTEST.
However this does not affect board testing.
2. In common with some other manufacturers, pin
TRST is internally pulled Low to disable JTAG by
default. The standard is to pull High . The polarity
of TRST is as the standard: TRST High to enable
JTAG boundary scan mode, TRST Low for normal
operation.
The JTAG timing diagram is shown in Figure 14 .
Figure 14 JTAG Timing
Over-voltage Protection
The ACS8514 may require Over-Voltage Protection on
input reference clock ports according to ITU
recommendation K.41[16]. Semtech protection devices are
recommended for this purpose (see separate Semtech
data book).
ESD Protection
Suitable precautions should be taken to protect against
electrostatic damage during handling and assembly. This
device incorporates ESD protection structures that protect
the device against ESD damage at ESD input levels up to
at least +/2kV using the Human Body Model (HBD) MIL-
STD-883D Method 3015.7, for all pins except pins 24 &
25 (AMI inputs) which are protected up to at least +/- 1kV.
Latchup Protection
This device is protected against latchup for input currents
pulses of magnitude up to at least +/- 100mA according
to JEDEC Standard No.78 August 1997.
Table 20 JTAG Timing (for use with Figure 14 )
Parameter
Cycle Time
TMS/TDI to TCK rising edge time
TCK rising to TMS/TDI hold time
TCK falling to TDO valid
Symbol
tCYC
tSUR
tHT
tDOD
Minimum
50
3
23
-
Typical
-
-
-
-
Maximum
-
-
-
5
Units
ns
ns
ns
ns
Revision 3.00 April 2007 © Semtech Corp.
Page 73
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