ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 21
Register Name cnfg_ref_source_frequency
_2
FINAL
Description
(R/W) Configuration of the
frequency and input monitoring
for input I2.
DATASHEET
Default Value 0000 0000
Bit 7
Bit 6
Set to zero
Bit 5
Bit 4
bucket_id_2
Bit 3
Bit 2
Bit 1
Set to zero
Bit 0
Bit No.
Description
Bit Value Value Description
[7:6]
[5:4]
Set to zero
bucket_id_2
Every input has its own Leaky Bucket used for
activity monitoring. There are four possible
configurations for each Leaky Bucket- see Reg. 50
to Reg. 5F. This 2-bit field selects the configuration
used for input I2.
[3:0]
Set to zero
00
00
01
10
11
0000
Set to zero
Input I2 activity monitor uses Leaky Bucket
Configuration 0.
Input I2 activity monitor uses Leaky Bucket
Configuration 1.
Input I2 activity monitor uses Leaky Bucket
Configuration 2.
Input I2 activity monitor uses Leaky Bucket
Configuration 3.
8 kHz only
Address (hex): 22
Use <n> = 3
Register Name cnfg_ref_source_frequency
_<n>, where for Reg 22, n =
3
Description
(R/W) Configuration of the
frequency and input monitoring
for input I<n>.
Default Value
0000 0000
Bit 7
divn_<n>
Bit 6
lock8k_<n>
Bit 5
Bit 4
bucket_id_<n>
Bit 3
Bit 2
Bit 1
reference_source_frequency_<n>
Bit 0
Bit No.
Description
Bit Value Value Description
7
divn_<n>
This bit selects whether or not input I<n> is divided
in the programmable pre-divider prior to being input
to the DPLL and frequency monitor- see Reg. 46
and Reg. 47 (cnfg_freq_divn).
6
lock8k_<n>
This bit selects whether or not input I<n> is divided
in the preset pre-divider prior to being input to the
DPLL. This results in the DPLL locking to the
reference after it has been divided to 8 kHz. This bit
is ignored when divn_<n> is set (bit =1).
0
Input I<n> fed directly to DPLL and monitor.
1
Input I<n> fed to DPLL and monitor via pre-divider.
0
Input I<n> fed directly to DPLL.
1
Input I<n> fed to DPLL via preset pre-divider.
Revision 3.02/October 2005 © Semtech Corp.
Page 77
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