ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 63
FINAL
DATASHEET
Register Name cnfg_output_frequency
(MFrSync)
Description
(R/W) Register to configure and Default Value
enable the frequencies available
on MFrSync output.
1100 0000
Bit 7
MFrSync_en
Bit 6
FrSync_en
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
7
6
[5:0]
MFrSync_en
Register bit to enable the 2 kHz Sync output
(MFrSync).
FrSync_en
Register bit to enable the 8 kHz Sync output
(FrSync).
Not used.
0
Output MFrSync disabled.
1
Output MFrSync enabled.
0
Output FrSync disabled.
1
Output FrSync enabled.
-
-
Address (hex): 64
Register Name cnfg_T4_DPLL_frequency
Description
(R/W) Register to configure the T4 Default Value
DPLL and several other
parameters for the T4 path.
0000 0101
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T4_DPLL_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
[7:3]
[2:0]
Not used.
T4_DPLL_frequency
Register to configure the frequency of operation of
the DPLL in the T4 path. The frequency of the DPLL
will also affect the frequency of the T4 APLL which,
in turn, affects the frequencies available at outputs
O1 - O4 see Reg. 60 - Reg. 62. It is also possible to
not use the T4 DPLL at all, but use the T4 APLL to
run directly from the T0 DPLL output, see Reg. 65
(cnfg_TO_DPLL_frequency). If any frequencies are
required from the T4 APLL then the T4 DPLL should
not be squelched, as the T4 APLL input is squelched
and the T4 APLL will free run.
-
-
000
T4 DPLL squelched (clock off).
001
77.76 MHz (OC-N rates),
T4 APLL frequency = 311.04 MHz.
010
12E1, T4 APLL frequency = 98.304 MHz.
011
16E1, T4 APLL frequency = 131.072 MHz.
100
24DS1, T4 APLL frequency = 148.224 MHz.
101
16DS1, T4 APLL frequency = 98.816 MHz.
110
E3, T4 APLL frequency = 274.944 MHz.
111
DS3, T4 APLL frequency = 178.944 MHz.
Revision 1.00/September 2007 © Semtech Corp.
Page 87
www.semtech.com
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