ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 65
FINAL
DATASHEET
Register Name cnfg_T0_DPLL_frequency
Description
(R/W) Register to configure the T0 Default Value
DPLL and several other
parameters for the T0 path.
0000 0001
Bit 7
Bit 6
T4_meas_T0_ T4_APLL_for_
ph
T0
Bit 5
Bit 4
T0_freq_to_T4_APLL
Bit 3
Bit 2
Bit 1
T0_DPLL_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
7
6
[5:4]
3
[2:0]
T4_meas_T0_ph
Register bit to control the feature to use the T4 path
to measure phase offset from the T0 path. When
enabled the T4 path is disabled and the phase
detector is used to measure the phase between the
input to the T0 DPLL and the selected T4 input.
T4_APLL_for_T0
Register bit to select whether the T4 APLL takes its
input from the T4 DPLL or the T0 DPLL. If the T0
DPLL is selected then the frequency is controlled by
Bits [5:4], T0_freq_to_T4_APLL.
T0_freq_to_T4_APLL
Register to select the T0 frequency driven to the T4
APLL when selected by Bit 6, T4_APLL_for_T0.
Not used.
T0_DPLL_frequency
Register to configure the frequency of operation of
the DPLL/APLL in the T0 path. This register affects
the frequencies available at outputs O1 to O4, see
Reg. 60 - Reg. 63.
0
Normal- T4 Path normal operation.
1
T4 DPLL disabled, T4 phase detector used to
measure phase between selected T0 input and
selected T4 input.
0
T4 APLL takes its input from the T4 DPLL.
1
T4 APLL takes its input from the T0 DPLL.
00
12E1, T4 APLL frequency = 98.304 MHz.
01
16E1, T4 APLL frequency = 131.072 MHz.
10
24DS1, T4 APLL frequency = 148.224 MHz.
11
16DS1, T4 APLL frequency = 98.816 MHz.
-
-
000
77.76 MHz, digital feedback,
T0 APLL frequency = 311.04 MHz.
001
77.76 MHz, analog feedback,
T0 APLL frequency = 311.04 MHz.
010
12E1, T0 APLL frequency = 98.304 MHz.
011
16E1, T0 APLL frequency = 131.072 MHz.
100
24DS1, T0 APLL frequency = 148.224 MHz.
101
16DS1, T0 APLL frequency = 98.816 MHz.
110
Not used.
111
Not used.
Address (hex): 66
Register Name cnfg_T4_DPLL_bw
Bit 7
Bit 6
Bit 5
Bit No.
[7:2]
Description
Not used.
Description
Bit 4
(R/W) Register to configure the Default Value 0000 0000
bandwidth of the T4 DPLL.
Bit 3
Bit 2
Bit 1
Bit 0
T4_DPLL_bandwidth
Bit Value Value Description
-
-
Revision 1.00/September 2007 © Semtech Corp.
Page 88
www.semtech.com
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