ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 66 (cont...)
FINAL
Register Name cnfg_T4_DPLL_bw
Description
(R/W) Register to configure the
bandwidth of the T4 DPLL.
DATASHEET
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T4_DPLL_bandwidth
Bit No.
Description
Bit Value Value Description
[1:0]
T4_DPLL_bandwidth
00
T4 DPLL 18 Hz bandwidth.
Register to configure the bandwidth of the T4 DPLL.
01
T4 DPLL 35 Hz bandwidth.
10
T4 DPLL 70 Hz bandwidth.
11
Not used.
Address (hex): 67
Register Name cnfg_T0_DPLL_locked_bw
Description
(R/W) Register to configure the Default Value
bandwidth of the T0 DPLL, when
phase locked to an input.
0000 1101
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T0_DPLL_locked_bandwidth
Bit 0
Bit No.
Description
Bit Value Value Description
[7:4]
[3:0]
Not used.
-
-
T0_DPLL_locked_bandwidth
Register to configure the bandwidth of the T0 DPLL
when locked to an input reference. Reg. 3B Bit 7 is
used to control whether this bandwidth is used all of
the time or automatically switched to when phase
locked.
1000
T0 DPLL 0.1 Hz locked bandwidth.
1001
T0 DPLL 0.3 Hz locked bandwidth.
1010
T0 DPLL 0.6 Hz locked bandwidth.
1011
T0 DPLL 1.2 Hz locked bandwidth.
1100
T0 DPLL 2.5 Hz locked bandwidth.
1101
T0 DPLL 4 Hz locked bandwidth.
1110
T0 DPLL 8 Hz locked bandwidth.
1111
T0 DPLL 18 Hz locked bandwidth.
0000
T0 DPLL 35 Hz locked bandwidth.
0001
T0 DPLL 70 Hz locked bandwidth.
All other values Not used.
Revision 1.00/September 2007 © Semtech Corp.
Page 89
www.semtech.com
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