ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
FINAL
Figure 8 Automatic Mode Control State Diagram (DPLL1)
(1) Reset
Free-run
select ref
(state 001)
DATASHEET
(3) no valid standby ref
&
(main ref invalid
or out of lock > 100s
(2) all refs evaluated
&
at least one ref valid
Reference sources are flagged as valid when
active, in-band and have no phase alarm set.
(4) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock > 100s]
Pre-locked
wait for up to 100s
(state 110)
(5) selected ref
phase locked
All sources are continuously checked for
activity and frequency
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has been continuously in phase lock
for between 1 and 2 seconds.
(10) selected source
phase locked
Locked
keep ref
(state 100)
(6) no valid standby ref
&
main ref invalid
Pre-locked2
wait for up to 100s
(state 101)
(8) phase
(9) valid standby ref regained
&
within 100s
[main ref invalid or
(higher priority ref valid
& in revertive mode)]
(7) phase lost
on main ref
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
Lost-phase
wait for up to 100s
(state 111)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
Digital Holdover
select ref
(state 010)
(15) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
F8525D_018AutoModeContStateDia_01
Note...The state diagram above is for DPLL1 only, and the 3-bit state value refers to the register sts_operating Reg. 09 Bits
[2:0] DPLL1_operating _mode. By contrast, the DPLL2 has only automatic operation and can be in one of only two possible
states: “Instantaneous Automatic Holdover” with zero frequency offset (its start-up state), or “Locked”. The states of DPLL2
are not configurable by the User and there is no “Free-run” state.
Revision 1.00/September 2007 © Semtech Corp.
Page 31
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