ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
FINAL
DATASHEET
averaged or filtered with a -3 dB attenuation point at
with the DPLL1 PFD input reference signal. Reading the
approximately 100 Hz.
current phase register from DPLL2 will yield the filtered
phase difference between the two inputs. If there is jitter
Measuring Phase Between Master and
Slave/Stand-by SEC Sources
The phase can be measured between the selected SEC
input to DPLL1 and either of the other two SEC inputs by
or wander present on either or both inputs, then this will
have an effect on the measured phase. The extent of this
effect will depend on the frequency of the jitter/wander
compared to the 100 Hz bandwidth of the phase filter.
a using the Phase and Frequency detector of DPLL2. This With the input selections in the examples below, a
special configuration requires manual selection of
meaningful result for phase measurement will be
DPLL2’s selected source (by altering the Priorities).
obtained from Example 1 only.
The DPLL2 PFD compares two inputs (usually the
feedback and reference input) with each other and
performs some filtering. This filtering has a bandwidth of
approx. 100 Hz. This will result in a digital number
representing the filtered phase difference between these
two signals being available (normally used for the digital
synthesis).
Under normal circumstances the frequency of the inputs
to the PFD are determined by the input frequency
selection and the pre-divider settings such as lock8k and
DivN. The appropriate feedback frequency is
automatically selected from the supported spot
frequencies to match the input reference frequency (post
division if necessary).
The phase difference is reported in units of 0.707
degrees of the actual locking frequency. When direct
locking to high frequency input, the actual time is then
scaled down and will give resolution down to e.g. 110 ps
at 19.44 MHz in direct locking mode compared with
245 ns with Lock8K mode enabled with the same
19.44 MHz input. The two inputs to the PFD have to be
very close in frequency to give an accurate phase
measurement.
Reg. 65, Bit 7 is used to switch one input to the DPLL2
phase detector over to the current DPLL1 input. The other
phase detector input becomes connected to a second
input source. The second input source can be changed via
the DPLL2 priority (Reg. 19 to 1C), when Reg. 4B,
Bit 4 = 1).
The phase difference measurement is held in the 16-bit
register, sts_current_phase Reg. 77 and 78. The register
is updated on a 204.8 MHz cycle.
When measuring the relative phase error between the
selected inputs, the user must ensure that the settings
and frequency are the same for the two inputs to be
measured. Enabling this phase measurement feature
replaces the DPLL2 feedback signal to the DPLL2 PFD
Example 1
SEC1 19.44 MHz input, direct locking
SEC2 19.44 MHz input, direct locking
Example 2
SEC1 19.44 MHz input, direct locking
SEC2 19.44 MHz input, Lock8K
The phase reported in degrees of the locking frequency.
Direct locking to the highest frequency gives the most
meaningful result, as the actual time is scaled down and
will give a resolution in picoseconds, for example: 101 ps
@19.44 MHz, Direct locking on SEC1 and SEC2. With
Lock8K enabled instead of direct locking, a result can be
measured but the phase error will have a much lower
resolution of 245 nanoseconds.
Sync Reference Sources
The ACS8525A provides the facility to have a Sync
reference source associated with each SEC. The Sync
inputs (SYNC1, SYNC2 and SYNC3) are used for Frame
Sync output alignment and can be 2, 4 or 8 kHz
(automatically detected frequency). In the ACS8525A
device, the Sync is treated as an additional part of the SEC
clock. The failure of a Sync input will never cause a source
disqualification. The Sync input is used to internally align
the generation of the output 2 kHz and 8 kHz Sync pulses.
On the ACS8525A, the presence of a Sync input
associated with any particular SEC input is optional. If a
Sync input is not present, or it fails, the 2 kHz and 8 kHz
outputs will simply continue to be generated with the
same relationship to the SEC output. This also applies to
a source switch from a reference with a Sync input to a
reference without a Sync input. The Sync outputs are
always divided from the SEC outputs and will never
free-run.
Revision 1.00/September 2007 © Semtech Corp.
Page 33
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