ACS8525AP View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525AP' PDF : 112 Pages View PDF
ACS8525A LC/P
ADVANCED COMMS & SENSING
Address (hex): 06 (cont...)
FINAL
DATASHEET
Register Name sts_interrupts
Description
(R/W) Bits [15:8] of the interrupt Default Value 0011 1111
status register.
Bit 7
operating_
mode
Bit 6
DPLL1_
main_ref_failed
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
status_SEC3
Bit No.
Description
Bit Value Value Description
6
DPLL1_main_ref_failed
Interrupt indicating that input to the DPLL1 has
failed. This interrupt will be raised after 2 missing
input cycles. This is much quicker than waiting for
the input to become invalid. This input is not
generated in Free-run or Holdover modes. Latched
until reset by software writing a 1 to this bit.
0
Input to DPLL1 is valid.
1
Input to DPLL1 has failed.
Writing 1 resets the interrupt to 0.
[5:1]
Not used.
-
-
0
status_SEC3
0
Input SEC3 has not changed status (valid/invalid).
Interrupt indicating that input SEC3 has become
1
Input SEC3 has changed status (valid/invalid).
valid (if it was invalid), or invalid (if it was valid).
Writing 1 resets the interrupt to 0.
Latched until reset by software writing a 1 to this bit.
Address (hex): 07
Register Name sts_current_DPLL_frequency
[18:16]
Description
(RO) Bits [18:16] of the current Default Value 0000 0000
DPLL frequency.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits [18:16] of sts_current_DPLL_frequency
Bit No.
Description
Bit Value Value Description
[7:3]
[2:0]
Not used.
Bits [18:16] of sts_current_DPLL_frequency
When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B
(cnfg_registers_source_select) = 0 the frequency
for DPLL1 is reported.
When this Bit 4 = 1 the frequency for DPLL2 is
reported.
-
-
-
See register description of
sts_current_DPLL_frequency at Reg. 0D.
Revision 1.00/September 2007 © Semtech Corp.
Page 45
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