ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 48 (cont...)
Register Name cnfg_monitors
FINAL
DATASHEET
Description
(R/W) Configuration register
Default Value
controlling several input
monitoring and switching options.
0000 0100*
Bit 7
Bit 6
los_flag_on_
TDO
Bit 5
ultra_fast_
switch
Bit 4
ext_switch
Bit 3
PBO_freeze
Bit 2
PBO_en
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
4
ext_switch
Bit to enable external switching mode. When in
external switching mode, the device is only allowed
to lock to a pair of sources. If the programmed
priority of input SEC1 TTL is non-zero, then when the
SRCSW pin is High, the device will be forced to lock
to input SEC1 TTL regardless of the signal present
on that input. If the programmed priority of input
SEC1 TTL is zero, then it will be forced to lock to
input SEC1 DIFF instead. If the programmed priority
of input SEC2 TTL is non-zero, then when the
SRCSW pin is Low, the device will be forced to lock
to input SEC2 TTL regardless of the signal present
on that input. If the programmed priority of input
SEC2 TTL is zero, then it will be forced to lock to
input SEC2 DIFF instead.
* The default value of this bit is dependent on the
value of the SRCSW pin at power-up.
0
Normal operation mode.
1
External source switching mode enabled. Operating
mode of the device is always forced to be “locked”
when in this mode.
3
PBO_freeze
Bit to control the freezing of Phase Build-out
operation. If Phase Build-out has been enabled and
there have been some source switches, then the
input-output phase relationship of DPLL1 is
unknown. If Phase Build-out is no longer required,
then it can be frozen. This will maintain the current
input-output phase relationship, but not allow
further Phase Build-out events to take place. Simply
disabling Phase Build-out could cause a phase shift
in the output, as DPLL1 re-locks the phase to zero
degrees.
0
Phase Build-out not frozen.
1
Phase Build-out frozen, no further Phase Build-out
events will occur.
2
PBO_en
0
Phase Build-out not enabled. DPLL1 locks to zero
Bit to enable Phase Build-out events on source
degrees phase.
switching. When enabled a Phase Build-out event is
1
Phase Build-out enabled on source switching.
triggered every time DPLL1 selects a new source-
this includes exiting the Holdover or Free-run states.
1
Not used.
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Revision 3.01/August 2005 © Semtech Corp.
Page 67
www.semtech.com
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