ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 4B
Register Name cnfg_registers_source_select
FINAL
DATASHEET
Description
(R/W) Register to select the
Default Value 0000 0000
source of many of the registers.
Bit 7
Bit 6
Bit 5
Bit 4
DPLL1_DPLL2_
select
Bit 3
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:5]
4
[3:0]
Not used.
DPLL1_DPLL2_select
Bit to select between many of the registers
associated with DPLL1 or DPLL2 e.g. frequency
registers.
Not used.
-
-
0
DPLL1 registers selected.
1
DPLL2 registers selected.
-
-
Address (hex): 4D
Register Name cnfg_freq_lim_ph_loss
Description
(R/W) Register to enable the
Default Value
phase lost indication when DPLL
hits its hard frequency limit.
1000 1110
Bit 7
freq_lim_ph_
loss
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:0]
freq_lim_ph_loss
Bit to enable the phase lost indication when the
DPLL hits its hard frequency limit as programmed in
Reg. 41 and Reg. 42 (cnfg_DPLL_freq_limit). This
results in the DPLL entering the phase lost state any
time the DPLL tracks to the extent of its hard limit.
Not used.
0
Phase lost/locked determined normally.
1
Phase lost forced when DPLL tracks to hard limit.
-
-
Revision 3.01/August 2005 © Semtech Corp.
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