ACS8526P View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526P' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Figure 4 PLL Block Diagram
FINAL
DATASHEET
DPLL2
sts_current_phase
PFD and
Loop Filter
8 kHz
DPLL2_frequency
Forward
DFS
Feedback
DFS
DPLL2_dig_
feedback
1
0
DPLL1_freq_to_APLL2
0
MUX
2
1
APLL2
APLL2
Output
Dividers
01 and 02
DPLL1
8 kHz
DPLL1
Reference
Input
sts_current_phase
PFD and
Loop Filter
77M
Forward
DFS
DPLL1_frequency
1
LF
Output
0
DFS
0
MUX
1
1
DPLL1_frequency
APLL1
APLL3
APLL1
Output
Dividers
01 and 02
FrSync
MFrSync
O1 and O2
1
Feedback
Locking
DFS
Frequency
0
Analog
F8526D_017BLOCKDIA_01
DFS is a technique for generating an output frequency
using a higher frequency system clock (204.8 MHz in the
case of the 77.76 MHz synthesis). However, the edges of
the output clock are not ideally placed in time, since all
edges of the output clock will be aligned to the active edge
of the system clock. This means that the generated clock
will inherently have jitter on it equivalent to one period of
the system clock.
DPLL1 and APLLs
DPLL1 always produces 77.76 MHz. The input reference
is either passed directly to the PFD or via a pre-divider (not
shown) to produce the reference input. The feedback
77.76 MHz is either divided or synthesized to generate
the locking frequency.
The DPLL1 77M Forward DFS block uses DFS clocked by
the 204.8 MHz system clock to synthesize the 77.76 MHz
and, therefore, has an inherent 4.9 ns of p-p jitter. There
is an option to use a feedback APLL (APLL3) to filter out
this jitter before the 77.76 MHz is used to generate the
feedback locking frequency in the DPLL1 feedback DFS
block. This analog feedback option allows a lower jitter
(<1 ns) feedback signal to give maximum performance.
The 77.76 MHz is fed to DPLL1 LF Output DFS block and
to APLL1. The low frequency DPLL1 LF Output DFS block
is used to produce three frequencies; two of them,
Digital1 and Digital2, are available for selection to be
produced at outputs O1 and O2, and the third frequency
can produce multiple E1/DS1 rates via the filtering APLLs.
The input clock to the DPLL1 LF Output DFS block is
77.76 MHz from APLL1 (post jitter filtering) or 77.76 MHz
direct from the DPLL1 77M Forward DFS.
Utilizing the clock from APLL1 will result in lower jitter
outputs from the DPLL1 LF Output DFS block. However,
when the input to the APLL1 is taken from the DPLL1 LF
Output DFS block, the input to that block comes directly
from the DPLL1 77M Forward DFS block so that a “loop”
is not created.
APLL1 is for multiplying and filtering. The input to APLL1 is
controlled by MUX 1 (see “Multiplexers” on page 13). The
frequency from APLL1 is four times its input frequency i.e.
311.04 MHz when used with a 77.76 MHz input. APLL1 is
subsequently divided by 1, 2, 4, 6, 8, 12, 16 and 48 and
these are available at the O1 and O2 Outputs.
DPLL2 & APLLs
DPLL2 is simpler than DPLL1. DPLL2 offers no low
frequency output. The DPLL2 input can only be used to
lock to DPLL1. Unlike DPLL1, the DPLL2 Forward DFS
block does not always generate 77.76 MHz. The possible
Revision 4.01/June 2006 © Semtech Corp.
Page 12
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