ACS8526P View Datasheet(PDF) - Semtech Corporation
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Description
MFG CO.
'ACS8526P' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
FINAL
4. Refer to Table 13, O1 and O2 Output Frequency
Selection, and the column headings in Table 10,
Frequency Divider Look-up, to select the appropriate
frequency from either of the APLLs on each output as
required.
DATASHEET
Table 6 Output 01 Frequency Selection by Hardware Configuration
O1_FREQ
SONSDHB
Output
DPLL Selected
Pin
Frequency/
2
1
0
MHz
0
0
0
X
0
-
0
0
0
1
1
0
1
0
X
34.368
44.736
19.44
DPLL2
DPLL2
DPLL1
0
1
1
X
25.92
DPLL1
1
0
0
X
1
0
1
X
1
1
0
X
38.88
51.84
77.76
DPLL1
DPLL1
DPLL1
1
1
1
X
155.52
DPLL1
DPLL Mode
Jitter Level (typ)
rms (ps) p-p (ns)
-
-
-
E3
120
1
DS3
110
1
Analog feedback 60
0.6
Analog feedback 60
0.6
Analog feedback 60
0.6
Analog feedback 60
0.6
Analog feedback 60
0.6
Analog feedback 60
0.6
Table 7 Output 02 Frequency Selection by Hardware Configuration
O2_FREQ
SONSDHB O1_FREQ
Output
DPLL Selected DPLL Mode
Jitter Level (typ)
Pin
=
Frequency/
2
1
0
“001”
MHz
rms (ps) p-p (ns)
0
0
0
X
X
0
-
-
-
-
0
0
0
1
FALSE
1
0
0
0
1
TRUE
1
2.048
1.544
2.048
3.088
DPLL2
DPLL2
DPLL1
DPLL1
16E1
16DS1
12E1
24DS1
400
2
200
1.2
900
0.45
110
0.75
0
X
0
1
0
1
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
34.368
44.736
19.44
25.92
38.88
DPLL2
E3
120
1
DPLL2
DS3
110
1
DPLL1
Analog feedback
60
0.6
DPLL1
Analog feedback
60
0.6
DPLL1
Analog feedback
60
0.6
1
1
0
X
X
51.84
DPLL1
Analog feedback
60
0.6
1
1
1
X
X
77.76
DPLL1
Analog feedback
60
0.6
Revision 4.01/June 2006 © Semtech Corp.
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