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ACS8526P View Datasheet(PDF) - Semtech Corporation

Part Name
Description
MFG CO.
'ACS8526P' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
FINAL
Table 8 Output Reference Source Selection Table
Port
Name
Output Port
Technology
Frequencies Supported
Output
O1
Output
O2
LVDS/PECL
(LVDS default)
TTL/CMOS
Frequency selection as per Table 9 and Table 13
FrSync TTL/CMOS
FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.
MFrSync TTL/CMOS
MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.
DATASHEET
Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default. When High, SONET is default.
Table 9 Output Frequency Selection
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
DPLL2 Mode
APLL2 Input Mux Jitter Level (typ)
2 kHz
77.76 MHz Analog
-
rms p-p (ns)
(ps)
-
60 0.6
2 kHz
8 kHz
Any digital feedback
-
mode
77.76 MHz Analog
-
-
1400 5
-
60 0.6
8 kHz
1.536
1.536
Any digital feedback
mode
-
-
-
12E1 mode
-
-
1400 5
Select DPLL2
Select DPLL1 12E1
500 2.3
250 1.5
1.544
-
16DS1 mode
Select DPLL2
200 1.2
1.544
-
1.544 via Digital1 or Digital2 (not Output O1) 77.76 MHz Analog
1.544 via Digital1 or Digital2 (not Output O1) Any digital feedback
mode
2.048
-
2.048
-
2.048
-
-
-
-
12E1 mode
-
16E1 mode
Select DPLL1 16DS1 150 1.0
-
3800 13
-
3800 18
Select DPLL2
Select DPLL1 12E1
Select DPLL2
500 2.3
250 1.5
400 2.0
2.048
-
-
Select DPLL1 16E1 220 1.2
2.048 (not Output O1)
12E1 mode
2.048 via Digital1 or Digital2 (not Output O1) 77.76 MHz Analog
2.048 via Digital1 or Digital2 (not Output O1) Any digital feedback
mode
2.059
-
2.059
-
-
-
-
16DS1 mode
-
-
900 4.5
-
3800 13
-
3800 18
Select DPLL2
200 1.2
Select DPLL1 16DS1 150 1.0
Revision 4.01/June 2006 © Semtech Corp.
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