AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
0
10 20 30 40 50 60 70 80 90 100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 68. SDIO Pin Loading
AD9228
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK/DTP, and
SDIO/ODM pins. By disconnecting these pins from the control
bus, the ADC can function in its most basic operation. Each
of these pins has an internal termination that floats to its
respective level.
CSB
tDS
tS
tDH
tHI
tCLK
tLO
SCLK DON’T CARE
SDIO DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
tH
DON’T CARE
D5
D4
D3
D2
D1
D0
DON’T CARE
Table 15. Serial Timing Definitions
Parameter
Timing (Minimum, ns)
tDS
5
tDH
2
tCLK
40
tS
5
tH
2
tHI
16
tLO
16
tEN_SDIO
10
tDIS_SDIO
10
Figure 69. Serial Timing Details
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
Rev. B | Page 31 of 52
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