AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
AD9228
EVALUATION BOARD
The AD9228 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially using a
transformer (default) or an AD8332 driver. The ADC can also be
driven in a single-ended fashion. Separate power pins are provided
to isolate the DUT from the drive circuitry of the AD8332. Each
input configuration can be selected by changing the connection
of various jumpers (see Figure 73 to Figure 77). Figure 71 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9228. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.
See Figure 73 to Figure 81 for the complete schematics and
layout diagrams demonstrating the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board has a wall-mountable switching power
supply that provides a 6 V, 2 A maximum output. Connect the
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to
63 Hz. The other end of the supply is a 2.1 mm inner diameter
jack that connects to the PCB at P503. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L504 to L507 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P501 to connect a different supply for
each section. At least one 1.8 V supply is needed for AVDD_DUT
and DRVDD_DUT; however, it is recommended that separate
supplies be used for analog and digital signals and that each
supply have a current capability of 1 A. To operate the evaluation
board using the VGA option, a separate 5.0 V analog supply
(AVDD_5 V) is needed. To operate the evaluation board using
the SPI and alternate clock options, a separate 3.3 V analog
supply (AVDD_3.3 V) is needed in addition to the other
supplies.
INPUT SIGNALS
When connecting the clock and analog sources to the evaluation
board, use clean signal generators with low phase noise, such as
Rohde & Schwarz SMHU or HP8644B signal generators or the
equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable.
Enter the desired frequency and amplitude from the ADC speci-
fications tables. Typically, most Analog Devices evaluation boards
can accept approximately 2.8 V p-p or 13 dBm sine wave input
for the clock. When connecting the analog input source, it is
recommended to use a multipole, narrow-band, band-pass filter
with 50 Ω terminations. Good choices of such band-pass filters are
available from TTE, Allen Avionics, and K&L Microwave, Inc.
The filter should be connected directly to the evaluation board
if possible.
OUTPUT SIGNALS
The default setup uses the Analog Devices, Inc., HSC-ADC-
FPGA-4/HSC-ADC-FPGA-8 high speed deserialization board
to deserialize the digital output data and convert it to parallel
CMOS. These two channels interface directly with the Analog
Devices standard dual-channel FIFO data capture board (HSC-
ADC-EVALB-DC). Two of the four channels can then be evaluated
at the same time. For more information on the channel settings
and optional settings of these boards, visit www.analog.com/FIFO.
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
SWITCHING
POWER
SUPPLY
5.0V
1.8V
– +– +
1.8V
–+
3.3V
–+
3.3V
–+
1.5V
–+
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS XFMR
FILTER
INPUT
CLK
AD9228
EVALUATION BOARD
CH A TO CH D
12-BIT
SERIAL
LVDS
SPI
HSC-ADC-FPGA-4/
HSC-ADC-FPGA-8
HIGH SPEED
DESERIALIZATION
BOARD
2 CH
12-BIT
PARALLEL
CMOS
SPI
Figure 71. Evaluation Board Connection
3.3V
–+
HSC-ADC-EVALB-DC
FIFO DATA
CAPTURE
BOARD
USB
CONNECTION
SPI
PC
RUNNING
ADC
ANALYZER
AND SPI
USER
SOFTWARE
SPI
Rev. B | Page 36 of 52
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