AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
AD9228
Table 16. Memory Map Register
Addr.
(Hex) Register Name
(MSB)
Bit 7
Chip Configuration Registers
00
chip_port_config 0
Bit 6
LSB first
1 = on
0 = off
(default)
Bit 5
Bit 4
Soft
1
reset
1 = on
0 = off
(default)
Bit 3
1
Bit 2
Bit 1
(LSB)
Bit 0
Soft
LSB first 0
reset
1 = on
1 = on 0 = off
0 = off (default)
(default)
01
chip_id
8-bit Chip ID Bits [7:0]
(AD9228 = 0x02), (default)
02
chip_grade
X
Device Index and Transfer Registers
05
device_index_A X
FF
device_update X
Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
Clock
Clock
Channel Channel
DCO
FCO
1 = on 1 = on
0 = off 0 = off
(default) (default)
X
X
X
ADC Functions
08
modes
X
X
X
X
09
clock
X
X
X
X
0D
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
X
X
X
X
Data
Channel
D
1 = on
(default)
0 = off
X
Data
Channel
C
1 = on
(default)
0 = off
X
Data
Channel
B
1 = on
(default)
0 = off
X
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
X
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Default
Value
(Hex)
0x18
0x02
Read
only
0x0F
0x00
0x00
0x01
0x00
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
Turns the
internal duty
cycle stabilizer
on and off.
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
Rev. B | Page 33 of 52
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