AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
GENERAL DESCRIPTION
The AD9910 is a direct digital synthesizer (DDS) featuring
an integrated 14-bit DAC and supporting sample rates up to
1 GSPS. The AD9910 employs an advanced, proprietary DDS
technology that provides a significant reduction in power con-
sumption without sacrificing performance. The DDS/DAC
combination forms a digitally programmable, high frequency,
analog output synthesizer capable of generating a frequency
agile sinusoidal waveform at frequencies up to 400 MHz.
The user has access to the three signal control parameters that
control the DDS: frequency, phase, and amplitude. The DDS
provides fast frequency hopping and frequency tuning resolu-
tion with its 32-bit accumulator. With a 1 GSPS sample rate, the
tuning resolution is ~0.23 Hz. The DDS also enables fast phase
and amplitude switching capability.
The AD9910 is controlled by programming its internal control
registers via a serial I/O port. The AD9910 includes an integrated
static RAM to support various combinations of frequency, phase,
and/or amplitude modulation. The AD9910 also supports a user
defined, digitally controlled, digital ramp mode of operation. In
this mode, the frequency, phase, or amplitude can be varied
linearly over time. For more advanced modulation functions, a
high speed parallel data input port is included to enable direct
frequency, phase, amplitude, or polar modulation.
The AD9910 is specified to operate over the extended industrial
temperature range (see the Absolute Maximum Ratings section
for details).
2
SDIO
SCLK
I/O_RESET
CS
OSK
DRCTL 2
DRHOLD
DROVER
3
PROFILE
I/O_UPDATE
16
PARALLEL
INPUT
2
RAM_SWP_OVR
RAM
OUTPUT
SHIFT
KEYING
DIGITAL
RAMP
GENERATOR
PROGRAMMING
REGISTERS
8
DAC FSC
AD9910
DDS
8
DAC FSC
AUX
DAC
8-BIT
AMPLITUDE (A)
PHASE (θ)
A
Acos (ωt+θ)
DATA
θ
ROUTE FREQUENCY (ω)
AND
ω
PARTITION
Asin (ωt+θ)
CONTROL
CLOCK
INVERSE
SINC
FILTER
SYSCLK
÷2
INTERNAL CLOCK TIMING
AND CONTROL
PLL
DAC
14-BIT
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
POWER
DOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
2
2
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
XTAL_SEL
Figure 2. Detailed Block Diagram
Rev. 0 | Page 4 of 60
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