AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
Parameter
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY CURRENT
IAVDD (1.8 V)
IAVDD (3.3 V)
IDVDD (1.8 V)
IDVDD (3.3 V)
TOTAL POWER CONSUMPTION
Single Tone Mode
Rapid Power-Down Mode
Full Sleep Mode
Conditions/Comments
1 mA load
Min Typ Max Unit
2.0
V
0.8 V
90 120 μA
38 50
μA
2
pF
2.8
V
0.4 V
110
mA
29
mA
222
mA
11
mA
715 850 mW
330 400 mW
19 25
mW
1 The gain value for VCO range Setting 5 is measured at 1000 MHz.
2 Wake-up time refers to the recovery from analog power-down. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. The wake-
up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
Rev. 0 | Page 7 of 60
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