AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
Multichip Sync Register
Address 0x0A, 4 bytes are assigned to this register.
Table 25. Multichip Sync Register
Bit(s)
Descriptor
31:28
Sync Validation Delay
27
Sync Receiver Enable
26
Sync Generator Enable
25
Sync Generator Polarity
24
23:18
17:16
15:11
10:8
7:3
2:0
Not Available
Sync State Preset Value
Not Available
Output Sync Generator
Delay
Not Available
Input Sync Receiver Delay
Not Available
Explanation
This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the
delayed sync-in signal for the sync validation block in the sync receiver. Default is 00002.
0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 0000002.
This 5-bit number sets the output delay (in ~150 ps increments) of the sync generator.
Default is 000002.
This 5-bit number sets the input delay (in ~150 ps increments) of the sync receiver. Default
is 000002.
Digital Ramp Limit Register
Address 0x0B, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 26. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
Descriptor
Explanation
63:32
Digital Ramp Upper Limit 32-bit digital ramp upper limit value.
31:0
Digital Ramp Lower Limit 32-bit digital ramp lower limit value.
Digital Ramp Step Size Register
Address 0x0C, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 27. Bit Descriptions for Digital Ramp Step Size Register
Bit(s)
Descriptor
Explanation
63:32
Digital Ramp Decrement
Step Size
32-bit digital ramp decrement step size value.
31:0
Digital Ramp Increment
32-bit digital ramp increment step size value.
Step Size
Digital Ramp Rate Register
Address 0x0D, 4 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 28. Bit Descriptions for Digital Ramp Rate Register
Bit(s)
Descriptor
Explanation
31:16
Digital Ramp Negative
Slope Rate
16-bit digital ramp negative slope value that defines the time interval between decrement
values.
15:0
Digital Ramp Positive Slope 16-bit digital ramp positive slope value that defines the time interval between increment
Rate
values.
Rev. 0 | Page 58 of 60
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