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AD9910/PCBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
Profile Registers
There are eight consecutive serial I/O addresses (Address 0x0E
to Address 0x015) dedicated to device profiles. All eight profile
registers are either single tone profiles or RAM profiles. RAM
profiles are in effect when CFR1<31> = 1. Single tone profiles
are in effect when CFR1<31> = 0, CFR2<19> = 0, and CFR2<4>
= 0. In normal operation, the active profile register is selected
using the external PROFILE<2:0> pins. However, in the specific
case when CFR1<31> = 1 and CFR1<20:17> ≠ 00002, the active
profile is selected automatically (see the RAM Ramp Up
Internal Profile Control Mode section).
Profile 0 to Profile 7—Single Tone Register
Address 0x0E to Address 0x15, 8 bytes are assigned to this register.
Table 29. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register
Bit(s)
Descriptor
Explanation
63:62
Not Available
61:48
Amplitude Scale Factor
This 14-bit number controls the DDS output amplitude.
47:32
Phase Offset Word
This 16-bit number controls the DDS phase offset.
31:0
Frequency Tuning Word
This 32-bit number controls the DDS frequency.
Profile 0 to Profile 7—RAM Register
Address 0x0E to Address 0x15, 8 bytes are assigned to this register.
Table 30. Bit Descriptions for Profile 0 to Profile 7 RAM Register
Bit(s)
Descriptor
Explanation
63:56
Not Available
55:40
Address Step Rate
16-bit address step rate value.
39:30
Waveform End Address
10-bit waveform end address.
29:24
Not Available
23:14
Waveform Start Address
10-bit waveform start address.
13:6
Not Available
5
No-Dwell High
Effective only when the RAM mode is in ramp up.
0 = when the RAM state machine reaches the end address, it halts.
1 = when the RAM state machines reaches the end address, it jumps to the start address
and halts.
4
Not Available
3
Zero-Crossing
Effective only when in RAM mode, direct switch.
0 = zero-crossing function disabled.
1 = zero-crossing function enabled.
2:0
RAM Mode Control
See Table 13 for details.
Rev. 0 | Page 59 of 60
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