ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Pin No.
18, 19, 22, 23
20
24
25
26
27
28
29, 32
33, 34, 35
36
37
38
39
Mnemonic
VN, VCP, VBP,
VAP
REF_GND
AVDD
AGND
VDD
CLKIN
CLKOUT
IRQ0, IRQ1
CF1, CF2,
CF3/HSCLK
SCLK/SCL
MISO/HSD
MOSI/SDA
SS/HSA
EP
Description
Analog Inputs, Voltage Channels. These channels are used with the voltage transducer. The VN, VCP, VBP, and
VAP inputs are single-ended voltage inputs with a maximum signal level of ±0.5 V peak with respect to VN
for specified operation. Each voltage channel also has an internal PGA.
Ground Reference, Internal Voltage Reference. Connect REF_GND to the analog ground plane.
2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in
parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin.
Ground Reference for the Analog Circuitry. Tie AGND to the analog ground plane or to the quietest ground
reference in the system. Use this quiet ground reference for all analog circuitry, for example, antialiasing
filters, current transducers, and voltage transducers.
Supply Voltage. The VDD pin provides the supply voltage. In PSM0 (normal power) mode, maintain the supply
voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power) mode, PSM2 (low power) mode, and
PSM3 (sleep) mode, when the ADE7868A or ADE7878A is supplied from a battery, maintain the supply voltage
from 2.8 V to 3.7 V. Decouple VDD to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
The only power modes available on the ADE7858A and ADE7854A are the PSM0 and PSM3 modes.
Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal can be connected
across the CLKIN and CLKOUT pins to provide a clock source for the ADE7854A, ADE7858A, ADE7868A, or
ADE7878A. The clock frequency for specified operation is 16.384 MHz. For information about choosing a
suitable crystal, see the Crystal Circuit section.
Crystal Output. A crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for
the ADE7854A, ADE7858A, ADE7868A, or ADE7878A. The clock frequency for specified operation is
16.384 MHz. For information about choosing a suitable crystal, see the Crystal Circuit section.
Interrupt Request Outputs. These pins are active low logic outputs. For information about events that trigger
interrupts, see the Interrupts section.
Calibration Frequency Logic Outputs/Serial Clock Output of the HSDC Port. The CF1, CF2, and CF3/HSCLK
outputs provide power information based on the CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the
CFMODE register. Use these outputs for operational and calibration purposes. Scale the full-scale output
frequency by writing to the CF1DEN, CF2DEN, and CF3DEN registers (see the Energy to Frequency Conversion
section). CF3 is multiplexed with HSCLK.
Serial Clock Input for the SPI Port/Serial Clock Input for the I2C Port. All serial data transfers synchronize to
this clock (see the Serial Interfaces section). The SCLK/SCL pin has a Schmitt trigger input for use with a clock
source that has a slow edge transition time, for example, opto-isolator outputs.
Data Output for the SPI Port/Data Output for the HSDC Port.
Data Input for the SPI Port/Data Input and Output for the I2C Port.
Slave Select for the SPI Port/HSDC Port Active.
Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the
exposed pad to the pad on the PCB to confer mechanical strength to the package. Connect the pads to
AGND and DGND.
Rev. C | Page 15 of 96
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