ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
can be read/written without any restriction. The run register,
used to start and stop the DSP, is cleared to 0x0000; write
0x0001 to the run register to start DSP code execution.
To protect the integrity of the data stored in the data memory
RAM of the DSP (addresses between 0x4380 and 0x43BE), a
write protection mechanism is available. By default, the protec-
tion is disabled, and registers placed between 0x4380 and 0x43BE
can be written without restriction. When the protection is
enabled, no writes to these registers are allowed. Registers can
always be read without restriction, independent of the write
protection state.
–50 –40 –30 –20 –10 0 10 20 30 40 50
HOT TEMPERATURE COEFFICIENT (ppm/°C)
To enable the protection, write 0xAD to an internal 8-bit
register located at Address 0xE7FE, followed by a write of 0x80
Figure 60. Histogram of the Reference Drift from 25°C to 85°C
to an internal 8-bit register located at Address 0xE7E3.
Because the reference is used for all ADCs, any x% drift in the
reference results in a 2x% deviation of the meter accuracy. The
reference drift resulting from temperature changes is usually very
small and, typically, much smaller than the drift of other
Enable the write protection only after initializing the registers. If
any data memory RAM-based register must be changed, disable
the protection, change the value, and then reenable the protec-
tion. There is no need to stop the DSP to change these registers.
components on a meter.
To disable the protection, write 0xAD to an internal 8-bit
The ADE7854A/ADE7858A/ADE7868A/ADE7878A use the
internal voltage reference when Bit 0 (EXTREFEN) in the
register located at Address 0xE7FE, followed by a write of 0x00
to an internal 8-bit register located at Address 0xE7E3.
CONFIG2 register is cleared to 0 (the default value); the external
voltage reference is used when the bit is set to 1. Set the CONFIG2
register during the PSM0 mode; its value is maintained during the
PSM1, PSM2, and PSM3 power modes.
DIGITAL SIGNAL PROCESSOR
Use the following procedure to initialize the ADE7854A/
ADE7858A/ADE7868A/ADE7878A registers at power-up:
1. Initialize the AIGAIN, BIGAIN, CIGAIN, and NIGAIN
registers.
2. Initialize all the other data memory RAM registers. Write
The ADE7854A/ADE7858A/ADE7868A/ADE7878A contain a
fixed function digital signal processor (DSP) that computes all
power and rms values. It contains program memory ROM and
data memory RAM.
The program used for the power and rms computations is
stored in the program memory ROM, and the processor executes
it every 8 kHz. The end of the computations is signaled by setting
Bit 17 (DREADY) to 1 in the STATUS0 register. To enable an
interrupt attached to this flag, set Bit 17 (DREADY) in the MASK0
register. When enabled, the IRQ0 pin is set low and the Status
Bit DREADY is set to 1 at the end of the computations. Writing
to the STATUS0 register with Bit 17 (DREADY) set to 1 clears the
status bit and sets the IRQ0 pin to high.
the last register in the queue three times to ensure that its
value was written into the RAM.
3. Initialize all of the other ADE7854A, ADE7858A,
ADE7868A, or ADE7878A registers with the exception of
the CFMODE register.
4. Enable the write protection by writing 0xAD to an internal
8-bit register located at Address 0xE7FE, followed by a write of
0x80 to an internal 8-bit register located at Address 0xE7E3.
5. Read back all data memory RAM registers to ensure that
they initialized with the desired values.
6. In the unlikely case that one or more registers did not initia-
lized correctly, disable the protection by writing 0xAD to
an internal 8-bit register located at Address 0xE7FE,
followed by a write of 0x00 to an internal 8-bit register
The registers used by the DSP are located in the data memory
located at Address 0xE7E3.
RAM, at addresses between 0x4380 and 0x43BE. The width of
a. Reinitialize the registers. Write the last register in the
this memory is 28 bits. Within the DSP core, the DSP contains a
queue three times.
two-stage pipeline. This means that when a single register must
b. Enable the write protection by writing 0xAD to an
be initialized, two more writes are required to ensure that the
internal 8-bit register located at Address 0xE7FE,
value has been written into RAM. If two or more registers must
followed by a write of 0x80 to an internal 8-bit register
be initialized, the last register must be written two more times
located at Address 0xE7E3.
to ensure that the value has been written into RAM.
7. Start the DSP by setting run = 1.
As explained in the Power-Up Procedure section, at power-up
or after a hardware or software reset, the DSP is in idle mode
and executes no instruction. All the registers located in the data
memory RAM are initialized at 0, their default values, and they
8. Read the energy registers (xWATTHR, xFWATTHR,
xVARHR, xFVARHR, and xVAHR) to erase their content
and start energy accumulation from a known state.
9. Clear Bit 9 (CF1DIS), Bit 10 (CF2DIS), and Bit 11
(CF3DIS) in the CFMODE register to enable pulses at
Rev. C | Page 42 of 96
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