ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
PMAX = 33,516,139, which is the instantaneous power
Average Power Data =
computed when the ADC inputs are at full scale and in phase.
Access the xWATT[23:0] waveform registers using various
serial ports (see the Waveform Sampling Mode section).
Fundamental Active Power Calculation—ADE7878A
Only
LPF2 Output
×
1 +
Watt
Gain Register
223
(28)
The output is scaled by −50% by writing 0xC00000 to the watt
gain registers, and it increases by +50% by writing 0x400000
to them. These registers calibrate the active power (or energy)
The ADE7878A computes the fundamental active power using
a proprietary algorithm that requires some initialization function of
calculation in the ADE7854A/ADE7858A/ADE7868A/
ADE7878A for each phase.
the frequency of the network and its nominal voltage measured in
the voltage channel. Bit 14 (SELFREQ) in the COMPMODE
register must be set according to the frequency of the network to
which ADE7878A is connected. Clear Bit 14 (SELFREQ) to 0
(the default value) when the network frequency is 50 Hz. Set
SELFREQ to 1 when the network frequency is 60 Hz. In addition,
initialize the VLEVEL 24-bit signed register with a positive value
based on the following expression:
As stated in the Current Waveform Gain Registers section,
the serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words, and the DSP
works on 28 bits. Similar to registers presented in Figure 34, the
AWGAIN, BWGAIN, CWGAIN, AFWGAIN, BFWGAIN, and
CFWGAIN 24-bit signed registers are accessed as 32-bit
registers with the four MSBs padded with 0s and sign extended
to 28 bits.
VLEVEL = VFS × 491,520
Vn
(27)
Active Power Offset Calibration
The ADE7854A/ADE7858A/ADE7868A/ADE7878A
where:
VFS is the rms value of the phase voltages when the ADC inputs
are at full scale.
Vn is the rms nominal value of the phase voltage.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7878A work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the registers in Figure 34,
the VLEVEL 24-bit signed register is accessed as a 32-bit register
with the four MSBs padded with 0s and sign extended to 28
bits.
Table 14 lists the settling time for the fundamental active power
measurement.
incorporate a watt offset, 24-bit register on each phase and on
each active power. The AWATTOS, BWATTOS, and CWATTOS
registers compensate the offsets in the total active power cal-
culations, and the AFWATTOS, BFWATTOS, and CFWATTOS
registers compensate offsets in the fundamental active power
calculations. These are signed twos complement, 24-bit registers
that remove offsets in the active power calculations.
An offset can exist in the power calculation caused by crosstalk
between channels on the PCB or in the chip itself. One LSB in
the active power offset register is equivalent to 1 LSB in the
active power multiplier output. At full-scale current and voltage
inputs, the LPF2 output is PMAX = 33,516,139. At −80 dB
down from the full scale (active power scaled down 104 times),
Table 14. Settling Times for Fundamental Active Power
63% Full-Scale Input Signals 100% Full-Scale Input Signals
one LSB of the active power offset register represents 0.0298%
of PMAX.
375 ms
875 ms
As stated in the Current Waveform Gain Registers section,
Active Power Gain Calibration
Note that the average active power result from the LPF2 output
in each phase can be scaled by ±100% by writing to the 24-bit
phase watt gain register (AWGAIN, BWGAIN, CWGAIN,
AFWGAIN, BFWGAIN, or CFWGAIN).
the serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words and the DSP works
on 28 bits. Similar to the registers shown in Figure 34, the
AWATTOS, BWATTOS, CWATTOS, AFWATTOS, BFWATTOS,
and CFWATTOS 24-bit signed registers are accessed as 32-bit
registers with the four MSBs padded with 0s and sign extended
By writing to the phase watt gain 24-bit register (AWGAIN,
to 28 bits.
BWGAIN, CWGAIN, AFWGAIN, BFWGAIN, or CFWGAIN),
the average active power result from the PDF2 output in each
phase is scaled by ±100%.
The xWGAIN registers are placed in each phase of the total
active power datapath, and the xFWGAIN (available for the
ADE7878A only) registers are placed in each phase of the
fundamental active power datapath. The watt gain registers are
twos complement, signed registers and have a resolution of
2−23/LSB. Equation 28 describes mathematically the function of
the watt gain registers.
Sign of Active Power Calculation
The average active power is a signed calculation. When the
phase difference between the current and voltage waveform is
more than 90°, the average power becomes negative. Negative
power indicates that energy is being injected back on the grid.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A have sign
detection circuitry for active power calculations and can monitor
the total active powers or the fundamental active powers. As
described in the Active Energy Calculation section, the active
energy accumulation occurs in two stages. Every time a sign
change is detected in the energy accumulation at the end of the
Rev. C | Page 49 of 96
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