ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
ADSP-21266
Power-Up Sequencing
The timing requirements for DSP startup are given in Table 10
and Figure 6.
Table 10. Power-Up Sequencing (DSP Startup)
Parameter
Min
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT On
0
tIVDDEVDD
VDDINT On Before VDDEXT
–50
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid1
0
tCLKRST
CLKIN Valid Before RESET Deasserted
102
tPLLRST
PLL Control Setup Before RESET Deasserted
203
Max
Unit
ns
200
ms
200
ms
µs
µs
Switching Characteristic
tCORERST
DSP Core Reset Deasserted After RESET Deasserted
4096tCK 4, 5
1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4097 cycles maximum.
RESET
VDDINT
VDDEXT
CLKIN
tRSTVDD
CLK_CFG1–0
RSTOUT*
tIVDDEVDD
tCLKVDD
tCLKRST
tPLLRST
tCORERST
*MULTIPLEXED WITH CLKOUT
Figure 6. Power-Up Sequencing
Rev. B | Page 18 of 44 | May 2005
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