ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
Clock Input
See Table 11 and Figure 7.
Table 11. Clock Input
Parameter
150 MHz
Min
Max
200 MHz
Min
Timing Requirements
tCK
CLKIN Period
201
tCKL
CLKIN Width Low
7.51
tCKH
CLKIN Width High
7.51
1602
151
802
61
802
61
tCKRF
CLKIN Rise/Fall (0.4 V – 2.0 V)
3
tCCLK
CCLK Period3
6.66
10
5
1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
CLKIN
t
CKH
tCK
t
CKL
Figure 7. Clock Input
Clock Signals
The ADSP-21266 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21266 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure 8 shows
the component connections used for a crystal operating in fun-
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
CLKIN
1M⍀
XTAL
C1
X1
C2
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Figure 8. 150 MHz or 200 MHz Operation with a 12.5 MHz
Fundamental Mode Crystal
Max
1602
802
802
3
10
ADSP-21266
Unit
ns
ns
ns
ns
ns
Rev. B | Page 19 of 44 | May 2005
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