ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
ADSP-21266
Reset
See Table 12 and Figure 9.
Table 12. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST
RESET Pulse Width Low1
4tCK
ns
tSRST
RESET Setup Before CLKIN Low
8
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
tWRST
tSRST
Figure 9. Reset
Interrupts
The timing specification in Table 13 and Figure 10 applies to the
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1
pins when configured as interrupts.
Table 13. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 Ă— tCCLK +2
Max
DAI_P20–1
(FLG2–0)
(IRQ2–0)
tIPW
Figure 10. Interrupts
Core Timer
The timing specification in Table 14 and Figure 11 applies to
FLAG3 when it is configured as the core timer (CTIMER).
Table 14. Core Timer
Parameter
Switching Characteristic
tWCTIM
CTIMER Pulse Width
Min
4 × tCCLK – 1
Max
Unit
ns
Unit
ns
FLG3
(C TIM ER)
tW C T IM
Figure 11. Core Timer
Rev. B | Page 20 of 44 | May 2005
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