ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
Memory Read—Parallel Port
The specifications in Table 20, Table 21, Figure 17, and
Figure 18 are for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21266 is access-
ing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
Min
Timing Requirements
tDRS
Address/Data 7–0 Setup Before RD High
3.3
tDRH
Address/Data 7–0 Hold After RD High
0
tDAD
Address 15–8 to Data Valid
Switching Characteristics
tALEW
ALE Pulse Width
tALERW
ALE Deasserted to Read/Write Asserted
tADAS
Address/Data 15–0 Setup Before ALE Deasserted1
tADAH
Address/Data 15–0 Hold After ALE Deasserted1
tALEHZ
ALE Deasserted1 to Address/Data[7:0] In High Z
tRW
RD Pulse Width
tADRH
Address/Data 15–8 Hold After RD High
D = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
2 × tCCLK – 2
1 × tCCLK – 0.5
2.5 × tCCLK – 2.0
0.5 × tCCLK – 0.8
0.5 × tCCLK – 0.8
D–2
0.5 × tCCLK – 1 + H
1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ADSP-21266
Max
D + 0.5 × tCCLK – 3.5
Unit
ns
ns
ns
ns
ns
ns
ns
0.5 × tCCLK + 2.0
ns
ns
ns
ALE
RD
WR
AD15-8
AD7-0
tALEW
tALERW
tRW
tADAS
tALEHZ
tADAH
tA D R H
VALID ADDRESS
VALID ADDRESS
tDRS
tDRH
VALID ADDRESS
tDAD
VALID DATA
Figure 17. 8-Bit Memory Read Cycle
Rev. B | Page 25 of 44 | May 2005
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