ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
Memory Write—Parallel Port
Use the specifications in Table 22, Table 23, Figure 19, and
Figure 20 for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21266 is access-
ing external memory space.
Table 22. 8-Bit Memory Write Cycle
Parameter
Switching Characteristics
tALEW
ALE Pulse Width
tALERW
ALE Deasserted to Read/Write Asserted
tADAS
Address/Data 15–0 Setup Before ALE Deasserted1
tADAH
Address/Data 15–0 Hold After ALE Deasserted1
tWW
WR Pulse Width
tADWL
Address/Data 15–8 to WR Low
tADWH
Address/Data 15–8] Hold After WR High
tALEHZ
ALE Deasserted1 to Address/Data 15–0 In High Z
tDWS
Address/Data 7–0 Setup Before WR High
tDWH
Address/Data 7–0 Hold After WR High
tDAWH
Address/Data to WR High
D = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Min
2 × tCCLK – 2
1 × tCCLK – 0.5
2.5 × tCCLK – 2.0
0.5 × tCCLK – 0.8
D–2
0.5 × tCCLK – 1.5
0.5 × tCCLK – 1 + H
0.5 × tCCLK – 0.8
D
0.5 × tCCLK – 1.5 + H
D
ALE
WR
tALEW
tALERW
tDAWH
tWW
ADSP-21266
Max
Unit
ns
ns
ns
ns
ns
ns
ns
0.5tCCLK + 2.0
ns
ns
ns
ns
RD
AD15-8
AD7-0
tADAS
tALEHZ
tADAH
VALID ADDRESS
VALID ADDRESS
tADWL
tADWH
VALID ADDRESS
tD W S
tDWH
VALID DATA
Figure 19. 8-Bit Memory Write Cycle
Rev. B | Page 27 of 44 | May 2005
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