ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
ADSP-21266
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN
tDDTTE
tDDTIN
Data Enable from External Transmit SCLK1
Data Disable from External Transmit SCLK1
Data Enable from Internal Transmit SCLK1
1 Referenced to drive edge.
Min
Max
2
7
–1
Table 27. Serial Ports—External Late Frame Sync
Parameter
Min
Max
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 01
7
tDDTENFS
Data Enable for MCE = 1, MFD = 01
0.5
1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTLFSE
tDDTE/I
2ND BIT
LATE EXTERNAL TRANSMIT FS
DAI_P201
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
2ND BIT
tDDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P[20:1] PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
Figure 21. External Late Frame Sync1
1 This figure reflects changes made to support left-justified sample pair mode.
Unit
ns
ns
ns
Unit
ns
ns
Rev. B | Page 30 of 44 | May 2005
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