ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 28 and
Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P20–1 pins.
Table 28. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
tSISFS
FS Setup Before SCLK Rising Edge1
2.5
ns
tSIHFS
FS Hold After SCLK Rising Edge1
2.5
ns
tSISD
SData Setup Before SCLK Rising Edge1
2.5
ns
tSIHD
SData Hold After SCLK Rising Edge1
2.5
ns
tIDPCLKW
Clock Width
7
ns
tIDPCLK
Clock Period
20
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either
CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tIDPCLKW
SAMPLE EDGE
tSISFS
tSISD
tSIHFS
tSIHD
Figure 23. Input Data Port (IDP)
Rev. B | Page 32 of 44 | May 2005
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