ADSP-21266SKSTZ-1C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21266SKSTZ-1C' PDF : 44 Pages View PDF
ADSP-21266
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in Table 29
and Figure 24. PDAP is the parallel mode operation of
Channel 0 of the IDP. For details on the operation of the IDP,
see the IDP chapter of the ADSP-2126x Peripherals Manual.
Note that the most significant 16 bits of external PDAP data can
be provided through either the parallel port AD15–0 or the
DAI_P20–5 pins. The remaining four bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
tSPCLKEN
tHPCLKEN
tPDSD
tPDHD
tPDCLKW
tPDCLK
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1
Clock Width
Clock Period
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
7
ns
20
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tCCLK
ns
tPDSTRB
PDAP Strobe Pulse Width
1 × tCCLK – 1
ns
1 Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
DAI_P20–1
(P DA P _C LK)
DAI_P20–1
(PDAP_CLKEN)
DATA
SAMPLE EDGE
tPDCLKW
tPDCLK
tSPCLKEN
tPDSD
tH P C L K E N
tPDHD
DAI_P20–1
(PDAP _STR OBE)
tPDHLDD
tPDSTRB
Figure 24. Parallel Data Acquisition Port (PDAP)
Rev. B | Page 33 of 44 | May 2005
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