ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 14.
• The product of CLKIN and PLLM must never exceed 1/2
fVCO (max) in Table 14 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLD)
where:
fVCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
fINPUT = Input frequency to the PLL.
fINPUT = CLKIN when the input divider is disabled or
fINPUT = CLKIN ÷ 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12. All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to tPCLK. See the peripheral specific section
for each peripheral’s timing information.
Table 12. Clock Periods
Timing
Requirements
tCK
tCCLK
tPCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × tCCLK
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hard-
ware Reference.
CLKIN
XTAL
BUF
CLKIN fINPUT
DIVIDER
PMCTL
(INDIV)
PMCTL
(SDCKR)
PLL
LOOP
FILTER
VCO
PLL
MULTIPLIER
fVCO
PLL
DIVIDER
PMCTL
(2xPLLD)
fCCLK
PMCTL
(PLLBP)
CCLK
SDRAM
DIVIDER
DIVIDE PCLK
BY 2
PMCTL
(PLLBP)
SDCLK
CLK_CFGx/PMCTL (2xPLLM)
PCLK
CCLK
RESET
DELAY OF
4096 CLKIN
CYCLES
RESETOUT
CLKOUT (TEST ONLY)
Figure 4. Core Clock and System Clock Relationship to CLKIN
BUF
RESETOUT
CORERST
Rev. C | Page 18 of 52 | September 2009
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