ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
Clock Input
Table 14. Clock Input
Parameter
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
tCCLK2
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
fVCO
VCO Frequency
1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
2 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
Min
22.51
11.251
11.251
3.75
200
266 MHz
Max
100
45
45
6
10
800
CLKIN
tCKH
tCK
tCKL
Figure 6. Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a 16.67
MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 266 MHz). To achieve the full core
clock rate, programs need to configure the multiplier bits in the
PMCTL register.
CLKIN
C1
22pF
ADSP-2137x
R1
1M⍀*
Y1
16.67 MHz
XTAL
R2
47⍀*
C2
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
Unit
ns
ns
ns
ns
ns
MHz
Rev. C | Page 20 of 52 | September 2009
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