ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
Parameter
IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus)
Timing Requirements:
tIKR
MPLX9 Low Before Start of Read1
tIRP
Duration of Read1
Switching Characteristics:
tIKHR
MPLX9 High After Start of Read1
tIKDS
tIKDH
tIKDD
MPLX_BUS Data Setup Before MPLX9 Low
MPLX_BUS Data Hold After End of Read2
MPLX_BUS Data Disabled After End of Read2
tIRDE
MPLX_BUS Previous Data Enabled After Start of Read
tIRDV
tIRDH1
MPLX_BUS Previous Data Valid After Start of Read
MPLX_BUS Previous Data Hold After Start of Read (DM/PM1)3
tIRDH2
MPLX_BUS Previous Data Hold After Start of Read (PM2)4
NOTES
1Start of Read = MPLX7 Low and MPLX5 Low.
2End of Read = MPLX7 High or MPLX5 High.
3DM read or first half of PM read.
4Second half of PM read.
Min
0
15
0.5tCK – 7
0
0
2tCK – 5
tCK – 5
Max
15
14
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/ MPLX9 IACK
t IKR
t IKHR
/ MPLX7 IS
t IRP
/ MPLX6 IRD
t IRDE
t IKDS
t IKDH
/ MPLX_BUS IAD15–0
t IRDV
PREVIOUS
DATA
t IRDH
READ DATA
t IKDD
Figure 21. IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus)
REV. 0
–31–
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